IJSER Home >> Journal >> IJSER
International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 6    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 6,June 2012
Reduced SCEs in Fully Depleted Dual-Material Double-Gate (DMDG) SON MOSFET: Analytical Modeling and Simulation
Full Text(PDF, )  PP.144-148  
Author(s)
Saheli Sarkhel, Sounak Naha, Subir Kumar Sarkar
KEYWORDS
— Fully depleted, Double Gate (DG), Dual Material gate (DMG), Analytical Modeling, Short channel effects (SCEs), SON MOSFET, Two Dimensional Modeling. —
ABSTRACT
In this paper, a two dimensional analytical model of a fully depleted nano-scale dual material double gate (DMDG) SON MOSFET has been developed and performance comparison is made with single material double gate SON MOSFET. An expression for the electric field has also been developed. It is found that the introduction of the DMDG structure in a fully depleted SON MOSFET leads to reduction of short channel effects due to a step-function in the surface potential profile thereby improving device performance and enhances devices scalability some steps further with the extreme exploitation of the idea, threshold control by means of multiple material gate electrode
References
[1] S.Deb, N.B.Singh, D.Das, A.K.De, S.K.Sarkar, ―Analytical model of Threshold Voltage and Sub-threshold Slope of SOI and SON MOSFETs: A comparative study‖, Journal of Electron Devices, Vol. 8, pp. 300- 309, 2010.

[2] The International Technology Roadmap for Semiconductor, Emerging Research Devices, 2009.

[3] M.Current, S.Bebell, I.Malik, L.Feng, F.Henley, ―What is the future of sub-100nm CMOS: Ultrashallow junctions or ultrathin SOI ?‖, Solid State Technology, 2000; 43,.

[4] J.Pretet,S.Monfray,S.Cristoloveanu,T.Skotnicki, ―Silicon-on-Nothing MOSFETs: Performance, Short-Channel Effects, and Backgate Coupling‖, IEEE Transactions on Electron Devices, 2004; 51(2), 240-246.

[5] M.Jurczak,T.Skotnicki,M.Paoli,B.Tormen,J.Martins,J.Regolini, D.Dutartre,P.Roibot,D.Lenoble,R.Pantel,S.Monfray, ―Silicon-onNothing (SON)-an Innovative Process for Advanced CMOS‖, IEEE

Transactions on Electron Devices, 2000; 47(11), 2179-2187. [6] T.Sato,H.Nii,M.Hatano,K.Takenaka,H.Hayashi,K.Ishigo,T.Hirano, K.Ida,Y.Tsunashima, ―Fabrication of SON (Silicon on Nothing)- MOSFET and Its ULSI Applications‖, IEIC Technical Report,2002;102(178); (SDM2002 66-106);99-104.

[7] D.J.Frank, R.H.Dennard, E.Nowak, D.M.Solomon, Y.Taur, and H.Wong, ‖Devicescaling limits of Si MOSFETs and their application dependencies‖ , Proc. IEEE, vol.89,pp.259-288, 2001.

[8] G. Venkateshwar Reddy and M. Jagadesh Kumar , ― A New DualMaterial Double-Gate (DMDG) Nanoscale SOI MOSFET- Two Dimensional Analytical Modeling and Simulation, “ IEEE Trans. on Nanotechnology, Vol. 4, pp.260-268, /March 2005.

[9] A. Chaudhry and M. J. Kumar, "Controlling Short-channel Effects in Deep Submicron SOI MOSFETs for Improved Reliability: A Review", IEEE Trans. on Device and Materials Reliability, Vol.4, pp.99-109, March 2004.

[10] M. J. Kumar and A. Chaudhry, "Two-Dimensional Analytical Modeling of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET and Evidence for Diminished Short-Channel Effects", IEEE Tran. on Electron Devices, Vol.15, pp.569-574, April 2004.

[11] K. Goel, M. Saxena, M. Gupta, and R. S. Gupta, ―Modeling and simulation of a nanoscale three-region tri-material gate stack (TRIMGAS) MOSFET for improved carrier transport efficiency and reduced hotelectron effects,‖ IEEE Trans. Electron Devices, vol. 53, no. 7, pp. 1623–1633, Jul. 2006.

Untitled Page