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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 1    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 1,January 2012
FPGA Prototyping of Hardware Implementation of CORDIC Algorithm
Full Text(PDF, )  PP.189-194  
Author(s)
Er. Manoj Arora, Er. R S Chauhan, Er.Lalit Bagga
KEYWORDS
CORDIC; FPGA; Discrete Fourier Transform (DFT); Discrete Cosine transform (DCT); Iterative CORDIC; Pipelined CORDIC,SVD.
ABSTRACT
In 1959 J. E. Volder presents a new algorithm for the real time solution of the equations raised in navigation system. This algorithm was the best replacement of analog navigation system by the digital. CORDIC algorithm used for the fast calculation of elementary functions like multiplication, division, trigonometric functions, logarithmic function, and various conversions like conversion of rectangular to polar coordinate, conversion between BCD and binary coded information. In the present time CORDIC algorithm have a number of applications in the field of communication, 3-D graphics, signal processing and a lot more. This review paper presents the prototype of hardware implementation of CORDIC algorithm using Spartan –II series FPGA, with constraint to area efficiency and throughput architecture
References
[1] Jack E. Volder, “The CORDIC trigonometric computing technique,” IRE Trans. Electron Computers, vol. EC-8, pp. 330–334, Sept. 1959.

[2] Jack E. Volder,” The Birth of CORDIC “, Journal of VLSI Signal Processing 25, 101–105, 2000.

[3] Ramesh Bhakthavatchalu1, Parvathi Nair, Jismi.K, Sinith.M.S, “A Comparison of Pipelined Parallel and Iterative CORDIC Design on FPGA” 2010 5th International Conference on Industrial and Information Systems, ICIIS 2010, Jul 29 - Aug 01, 2010, India.

[4] OSKAR MENCER, LUC S ´EM´ERIA AND MARTIN MORF, “Application of Reconfigurable CORDIC Architectures”, Journal of VLSI Signal Processing Systems 24, 211–221, 2000.

[5] Pramod K. Meher, Javier Valls, Tso-Bing Juang, K. Sridharan and Koushik Maharatna, “50 Years of CORDIC: Algorithms, Architectures and Applications” IEEE transactions on circuits and systems—I: regular papers, vol. 56, no. 9, september 2009.

[6] J. Villalba, T. Lang, and E. Zapata, “Parallel compensation of scale factor for the CORDIC algorithm,” J. VLSI Signal Process., vol. 19, no. 3, pp. 227–241, Aug. 1998.

[7] E. Antelo, J. Villalba, J. D. Bruguera, and E. L. Zapatai, “High performance rotation architectures based on the radix-4 CORDIC algorithm,” IEEE Trans. Computers, vol. 46, no. 8, pp. 855–870, Aug. 1997.

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