IJSER Home >> Journal >> IJSER
International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 11    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 11,November 2012
Low Voltage Low Power High Speed Flash ADC with Multiplexer based code converter
Full Text(PDF, )  PP.846-850  
Author(s)
Prasadh Teppala, K. Praveen Kumar, Ch. Praveen Kumar
KEYWORDS
Analog-to-Digital converter, Comparator, Encoder, Flash ADC, Low Power , Low Voltage, Pipelining, Track and Hold
ABSTRACT
This paper presents a low voltage low power high speed flash analog-to-digital converter (ADC). The proposed flash ADC is pipelined using track and hold circuit and at the input and output latches of the code converter. A new digital code converter has be
References
[1] X. Jiang, Z. Wang amd M.F Chang, “A 2GS/s 6-b ADC in 0.18µm CMOS,” IEEE International Solid-State Circuits Conference, vol. 1, pp. 9-13, Feb. 2003

[2] M. Choi and A. Abidi, “A 6-b 1.3 Gsamples/s A/D converter in0.35 μm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 36, pp. 1847- 1858, Dec. 2001.

[3] P.C.S. Scholtens and M. Bertregt, “A 6-bit 1.6 Gsamples/s FlashADC in 0.18 µm CMOS using Averaging Termination,” IEEEJournal of Solid-State Circuits, Vol. 37, No. 12, December 2002.

[4] J.Yoo, D. Lee, K. Choi, and A. Tangel. "Future-Ready Ultrafast 8bit CMOS ADC for System-on-Chip Applications", In IEEE International ASIC/SOC Conference, pages 455-459, 2001.

[5] J.Yoo, K. Choi, and A. Tangel. “A 1-GSPS CMOS Flash A/D Converter for System -on-Chip Applications”, In IEEE Computer Society Workshop on VLSl, pp. 135-139, April 2001.

[6] J. Yoo, K. Choi, D. Lee. “Comparator Generation and Selection for Highly Linear CMOS Flash Analog-to-Digital Converter,” Journal of Analog Integrated Circuits and Signal Processing, 35(2-3), pp. 179-187, 2003.

[7] J. Yoo, K. Choi, and J. Ghaznavi, “Quantum voltage comparatorfor 0.07 μm flash A/D converters,” Proceedings of the IEEEComputer Society Annual Symposium on VLSI, pp. 20-21, Feb.2003

[8] M.Wang, C I H Chen, S.Radhakrishnan, “Low-Power 4-b 2.5 GSPS Pipelined Flash Analog-to-Digital Converter in 130nm”, in IEEE Instrumentation and measurement,pp1064-73, June 2007.

[9] D. Lee, J. Yoo, K. Choi and J. Ghaznavi, “Fat-tree encoder design for ultra-high speed flash analog-to-digital converters,” IEEE Midwest Symposium on Circuits and Systems, 2002.

[10] E. Säll and M. Vesterbacka, “A multiplexer based decoder for flash analog-to-digital converters,” Proc. TENCON 2004, Nov. 21-24, 2004.

Untitled Page