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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 7    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 7,July 2012
Design, Synthesis and FPGA-based Implementation of a 32-bit Digital Signal Processor
Full Text(PDF, )  PP.I07-114  
Author(s)
Tasnim Ferdous
KEYWORDS
Digital Signal Processor, VHDL, Two stage Pipeline, Single cycle MAC, Hazard handling, FPGA, Speed optimization
ABSTRACT
With the advent of personal computer, smart phones, gaming and other multimedia devices, the demand for DSP processors in semi-conductor industry and modern life is ever increasing. Traditional DSP processors which are special purpose (custom logic) logic, added to essentially general purpose processors, no longer tends to meet the ever increasing demand for processing power. Today FPGAs have become an important platform for implementing high-end DSP applications and DSP processors because of their inherent parallelism and fast processing speed. This design work models and synthesizes a 32 bit two stage pipelined DSP processor for implementation on a Xilinx Spartan-3E (XC3S500e) FPGA. The design is optimized for speed constraint. A hazard free pipelined architecture and a dedicated single cycle integer Multiply-Accumulator (MAC) contribute in enhancing processing speed of this design. The design maintains a restricted instruction set, and consists of four major components: 1) the hazard free speed optimized Control unit, 2) a two stage pipelined data path, 3) a single cycle multiply and accumulator (MAC) and 4) a system memory. Harvard architecture is used to improve the processor's performance as both memories (program and data memory) are accessed simultaneously. The complete processor design has been defined in VHDL. Functionalities of designed processor are verified through Functional Simulation using Modelsim SE 6.5 simulator. The design is placed and routed for a Xilinx Spartan-3E FPGA.
References
[1] M. E. A. Ibrahim, M. Rupp , and H.A. H. Fahmy, “Power Estimation Methodology for VLIW Digital Signal Processors,” Proc. ACSSC, 2008.

[2] V. Gnatyuk and C. Runesson, “A Multimedia DSP processor design”, M.S. Thesis, Department of Electrical and Electronics, Linkoping University, Sweden, 2004.

[3] K. Karuri and R. Leupers, Application Analysis Tools for ASIP Design: Application Profiling and Instruction-set Customization, 1st ed., Springer, pp. 6-11, 2011.

[4] D. Skolnick and N. Levine, “An Introductory Course in DSP System Design,” Analog devices, http://www.analog.com/library/analogDialogue/archives/31-1/DSP.html. 1997

[5] “Xilinx Spartan-3 FPGA Family Data Sheet,” Product Specification DS312, Xilinx, Calif, Nov. 2006.

[6] A Primer on FPGA-based DSP Applications, Trends, Options, Considerations, and Tools for Using Re-configurable FPGA Platforms as an Alternative to Dedicated DSP Hardware, White Paper, Acromag, Wixom, MI, May, 2008.

[7] D. Zaretsky, M. Mittal, T. Xiaoyong , P. Banerjee, “Overview of the FREEDOM compiler for mapping DSP software to FPGAs,” Proc. FCCM, p.37, 2004.

[8] I. Kuon and J. Rose, “Measuring the Gap Between FPGAs and ASICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, pp. 203-215, Feb. 2007, doi: 10.1109/TCAD.2006.884574.

[9] J. Cong, B. Xiao, “mrFPGA: A Novel FPGA Architecture withMemristor-Based Reconfiguration,” Proc. ACM International Symp. Nanoscale Architectures, pp. 1-8,July 2011,doi: 10.1109/NANOARCH.2011.5941476

[10] C.-J. Chou, S. M. krishnan and J. B. Evans, “FPGA implementation of digital filters,” Proc. ICSPAT, 1993

[11] J. Becker, M. Glesner, “A Parallel Dynamically Reconfigurable Architecture Designed for Flexible Application-Tailored Hardware/Software Systems in Future Mobile Communication”, The Journal of Supercomputing, vol.19, no.1,pp. 105-127,May 2001.

[12] M. Ghosh, “Design and implementation of different multipliers using VHDL,” B.S. Thesis, Department of Electrical and Electronics, National Institute of Technology, Rourkela, India, 2007.

[13] K. Anand and S. Gupta, “Designing Of Customized Digital Signal Processor” B.T. Thesis, Department of Electrical and Electronics, Indian Institute of Technology, Delhi, 2007.

[14] Chattopadhyay, W. Ahmed, K. Karuri, D. Kammler, R. Leupers, G. Ascheid, H. Meyr, “Design Space Exploration of Partially Re-configurable Embedded Processors,” Proc. Design, Automation & Test in Europe Conference & Exhibition, p.319, 2007.

[15] C. Li, L. Xiao, Q. Yu, P. Gillard and R. Venkatesan, "Design of a Pipelined DSP Processor - MUN DSP2000,"Proc. NECEC, 2000.

[16] J. Treichler,Retrieved from the Connexions., http://cnx.org/content/col10553/1.3/. 2009.

[17] A. N. Sloss, D. Symes and C. Wright, “ARM System Developer’s Guide Designing and Optimizing System Software,” 1st ed., Morgan Kaufmann, pp. 9-14, 2004.

[18] M. R.S. Balpande, M.R.S. Keote, “Design of FPGA based Instruction Fetch & Decode Module of 32-bit RISC (MIPS) Processor,” Proc. ICCSNT, p. 409, 2011.

[19] Altium PPC405A 32-bit RISC Processor, Product Specification Core Reference CR0156 (V 2.0), Altium, Shanghi, July 2006.

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