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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 6    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 6,June 2012
An NoC Architecture with GA based Technique[
Full Text(PDF, )  PP.826-829  
Alamuri Khadar Basha, Patnala Madhu kumar
s Design Automation, Genetic Algorithms, Network-on-Chip (NoC), Pareto curve, Power consumption, Routing, Silicon-on-Chip (SoC)
In olden days, the communication between different IP cores in System-on-Chip (SoC) was point-to-point communication. Due to this point-to-point communication the interconnection wires between IP cores were more in number. To overcome these disadvantages a new SoC paradigm introduced. i.e. Network-on-Chip (NoC). Network-on-chip (NoC) architecture is regarded as a solution for future on-chip interconnects. However, the performance advantages of conventional NoC architectures are limited by the long latency and high power consumption due to multi-hop long distance communication among processing elements. To solve these limitations, we employed GA Technique on-chip communication as express links for transferring data so that transfer latency can be reduced. Network-on-chip (NoC) is an approach to design communication subsystem between IP cores in a System-on-Chip (SoC). This paper presents a genetic algorithm-based automated design technique that synthesizes an application specific NoC topology and routes the communication traces on the interconnection network. Genetic Algorithm based technique operates on the system-level floorplan of the system-on-chip (SoC) and accounts for the power consumption in the physical links and the routers. The design technique solves a multi-objective problem of minimizing the power consumption and the router resource.
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[4] ST Microelectronics, Geneva, Switzerland, “ST network onchip, “2005[online}.

[5] K. Srinivasan, K.S. Chatha, and G. Konjevod, “Linear programming based techniques for synthesis of network-onchip architectures, “IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 4, pp. 407-420, Apr. 2006

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