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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 6    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 6,June 2012
Area Reduction and Doubling the Speed of FIR Filter using VHDL
Full Text(PDF, )  PP.788-791  
K.V.N.M.Brahmanandam, V.Satya Deepthi, P.Durga Bhavani, U.Prathibha, M.Mani Divya
FPGA, FDA tool box, MATLAB, Multiple Constants Multiplications, Mac, Optimization, VHDL
The Finite Impulse Response (FIR) filter is a digital filter widely used in Digital Signal Processing applications in various fields like maging, instrumentation, and communications. This work proposes an VHDL generation software for FIR filters. In this paper a near algorithm for constant coefficient FIR filters was used. This algorithm uses general coefficient representation for the sharing of partial products in Multiple Constants Multiplications (MCM). The FIR filter is simulated with the help of Xilinx ISE (Integrated Software Environment). Codes for direct form fixed point FIR filter have been realized. Modules such as multiplier, adder, ram and two's compliment were used. For an N order filter the number of shift register and adders required is N and the number of multipliers required is N+1.These filters can work in real time. The software produces a generic VHDL output, synthesizable to FPGA.
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