IJSER Home >> Journal >> IJSER
International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 6    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 6,June 2012
Area Reduction and Doubling the Speed of FIR Filter using VHDL
Full Text(PDF, )  PP.788-791  
Author(s)
K.V.N.M.Brahmanandam, V.Satya Deepthi, P.Durga Bhavani, U.Prathibha, M.Mani Divya
KEYWORDS
FPGA, FDA tool box, MATLAB, Multiple Constants Multiplications, Mac, Optimization, VHDL
ABSTRACT
The Finite Impulse Response (FIR) filter is a digital filter widely used in Digital Signal Processing applications in various fields like maging, instrumentation, and communications. This work proposes an VHDL generation software for FIR filters. In this paper a near algorithm for constant coefficient FIR filters was used. This algorithm uses general coefficient representation for the sharing of partial products in Multiple Constants Multiplications (MCM). The FIR filter is simulated with the help of Xilinx ISE (Integrated Software Environment). Codes for direct form fixed point FIR filter have been realized. Modules such as multiplier, adder, ram and two's compliment were used. For an N order filter the number of shift register and adders required is N and the number of multipliers required is N+1.These filters can work in real time. The software produces a generic VHDL output, synthesizable to FPGA.
References
[1] http://www.dsptutor.freeuk.com/dfilt1.htm

[2] Carmelina Ruggiero, .SEGNALI BIOMEDICI 1. Laboratorio MedInfo

[3] .An Introduction to Digital Filters. by INTERSIL, Application Note, January 1999

[4] Ifeachor E.C., Jervis B.W., .Digital Signal Processing.,2nd Edition, Low Price Edition 2007.

[5]http://www.Xilinx.com/bvdocs/whitepapers/wp116.pdf.

[6] Jones D. L., .FIR Filter Structures., Version 1.2: Oct 10, 2004.

[7] Perry D., .VHDL., 3rd Edition, Tata Mc. Graw Hill Publications, 2001.

[8] Bhaskar J., .VHDL primer. ,3rd Edition, Pearson Education Asia Publications,2000

[9] Chen W. K., . Logic Design.,CRC Press, 2000.

[10] Wakerly J. F., .Digital Design & Practice.; Pearson Education Asia 3rd edition

[11] .FPGA Architect - XilinxXC4000/Spartan. by ELANIX Inc.

[12] Burrus C S, .Digital Filters Structures described by Distributed Arithmetic., IEEE Transactions on Circuits and Systems, vol. CAS-24, page: 12, December 1977.

[13] http://en.wikipedia.org/wiki/floating_point

[14] Parhi K K., .A Systematic Approach for Design of Digit-serial Signal Processing Architectures., Circuits and Systems, 1991.

[15] Prokis J. G., Manolakis D. G., .Digital Signal Processing. 3rd Edition, PHI publication 2004.

[16] Antoniou A.,. Digital Filter., 3rd Edition, Tata Mc. Graw Hill publications, 2001.

[17] Mitra S. K., .Digital Signal Processing. 3rd Edition, Tata Mc. Graw Hill Publications.

[18] Chapman S. J., . Matlab Programming for Engineers., 3rd Edition, Thomson learning 2005.

[19] Lee H., Sobelman G E. .Performance Evaluation and Optimal design for FPGAbased Digit-serial DSP Functions.. Computers and Electrical Engineering 29 ,2003

[20] Mirzaei S., Hosangadi A. and Kastner R. , .FPGA Implementation of High Speed FIR Filters Using Add and Shift Method., International Conference on Computer Design (ICCD ),pp 308-313, 2006

[21] Takahashi Y. and Yokoyama M., .New cost-effective VLSI implementation of multiplier less FIR filter using common subexpression elimination., Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS 2005), pp.845.848, May 2005.

[22] Rocha Ed., .Implementation trade-offs of digital FIR filters,. Military Embeded System, open system publishing,2007.

[23] Choi, Seak C. and Lee H., .A Partial Self-Reconfigurable Adaptive FIR Filter System,. signal processing systems,pp.204-209,2007.

Untitled Page