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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 6    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 6,June 2012
A Simulation Based Evaluation of Different Compressors For Fast Multiplication[
Full Text(PDF, )  PP.762-765  
Author(s)
Nilay Nagdeve, Vishal Moyal, Ms. Archana Fande
KEYWORDS
— Compressor; Analysis; Multiplier; Modified Booth’s; adders; fast; performance
ABSTRACT
In this paper, a comparison between different compressors is presented. A proper compressor selection approach to get minimum XOR delay is also shown. Again Booth's Modified Algorithm can be use for signed multiplication to get reduced partial products after which these compressors or a network of compressors can be used. This paper will help to choose a proper compressor for higher multiplication.
References
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[2] A New Multiplication Algorithm Using High-Speed Counters. Assady, P. 2009. 2009, European Journal of Scientific Research, pp. 362-368.

[3] Pallavi Devi Gopineedi, Hamid R. Arabnia. 2012. Novel and Efficient 4:2 and 5:2 Compressors with Minimum number of Transistors Designed for Low-Power Operations. Georgia : Athens, 2012.

[4] Low Power CMOS Pass Logic 4-2 Compressor for High-Speed Multiplication. D. Radhakrishnan, A.P. Preethy, Singapore, 2000

[5] G.M. Blair, “Designing Low Power CMOS”, IEEE Electronics and Communication Engineering Journal, vol. 6, pp. 229-236, 1994.

[6] Z. Wang, G. A. Jullien and W. C. Miller, “A new design technique for column compression multipliers,” in trans. Comput., vol. 44, pp. 962-970, Aug. 1995.

[7] K. Prasad and K. K. Parhi, “Low-power 4-2 and 5-2 compressors,” in proc.signals,systems and computers, vol. 1, pp. 129-133, Nov. 2001

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