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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 4    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 4,April 2012
Non-Restoring Divider Circuit Using a MCIT Based Adder Cell having Low Energy and High Speed Array
Full Text(PDF, )  PP.129-137  
Owk Prasanth Kumar
CAS, CMOS, Logic gates, MCIT, Multiplexing, Propagation delay, Shannon theorem
The paper discusses the design of 1-bit full adder circuit using MCIT. This proposed full adder circuit is used as one of the circuit component for implementation of Non- Restoring divider circuits. The proposed adder and divider schematics are designed by using SPICE and their layouts are generated. The divider circuits are designed by using standard NMOS and PMOS 180nm feature size and corresponding power supply 1.8 V. The parameters analyses are carried out by HSPICE analysis. We have compared the simulated results of the Shannon based divider circuit with CMOS adder cell based divider circuits. We have further compared the results with published results and observed that the proposed adder cell based divider circuit dissipates lower power, gives faster response
1. “Low Energy, Low Latency and High Speed Array Divider Circuit Using a Shannon Theorem Based Adder Cell” Chinnaiyan Senthilpari, Krishnamoorthy Diwakar and Ajay K. Singh- Recent Patents In Nano Technology, 2009 .

2. H.H.Guild-“Some cellular logic arrays for non-restoring division”.(The Radio and Electronic Engineer,Vol 39,1970.)

3. “An augumented iterative array for high speed binary division” Marus Cappa and V.Carl Hamacher IEEE Transactions of computers,Volc22,no:2, ,1973

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