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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 3    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 3,March 2012
Design of Router Architecture Based on Wormhole Switching Mode for NoC
Full Text(PDF, )  PP.87-91  
Author(s)
L.Rooban, S.Dhananjeyan
KEYWORDS
Network on chip, router architecture, wormhole switching
ABSTRACT
Network on Chip (NoC) is an approach to designing communication subsystem between intelligent property (IP) cores in a system on chip (SoC). Packet switched networks are being proposed as a global communication architecture for future system-on-chip (SoC) designs. In this project, we propose a design and implement a wormhole router supporting multicast for Network-on-chip. Wormhole routing is a network flow control mechanism which decomposes a packet into smaller flits and delivers the flits in a pipelined fashion. It has good performance and small buffering requirements. The implementations are at the RT level using VHDL and they are synthesizable. First, based on virtual cut through router model, a unicast router is implemented and validated and based on the wormhole switching mode the multicast router architecture is designed and implemented. A Wormhole input queued 2-D mesh router is created to verify the capability of our router
References
[1] A Modular Router Architecture Design for network on chip - a conference paper on system signals& devices

[2] Adaptive system on a chip (ASOC): A backbone for poweraware signal processing cores. Andrew Laffely, Jian Liang, Russell Tessier, Wayne Burleson.

[3] W. J. Dally, Virtual-channel flow control, inProc. 17th Annu. Int. Symp. Comput. Architecture, May 1990.

[4] S. Felperin, P. Raghavan, and E. Upfal, A theory of wormhole Routing, Proceeding IEEE Transaction on Computer, June 1996, Vol. 45, no. 6, Pages: 704-713.

[5] Fundamentals of digital logic with VHDL design, Stephen Brown, McGraw-Hill Higher Education, 2004.

[6] VHDL programming by example, Douglas L. Perry, McGraw-Hill, 2002.

[7] F. Moraes, N. Calazans, A. Mello, L. M. oller, and L. Ost, HERMES: an infrastructure for low area overhead packet switching networks on chip, INTEGRATION, the VLSI journal 2004. VOL.38,Pages:

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