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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 3    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 3,March 2012
Design of Low power, Low Jitter Ring Oscillator Using 50nm CMOS Technology
Full Text(PDF, )  PP.236-240  
Author(s)
Nidhi Thakur
KEYWORDS
Voltage Controlled Oscillator (VCO), power dissipation, jitter, tuning range, phase locked loop (PLL)
ABSTRACT
A modified ring oscillator presented in this paper. The voltage control oscillator is designed and simulated in 50nm CMOS technology. The frequency of oscillation of the VCO is 2.6GHz with 0.064 mW power dissipation and the center drain current of 64uA is used. Tuning range is of 72% and the jitter is of 39.8pS.
References
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