IJSER Home >> Journal >> IJSER
International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 3    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 3,March 2012
Design of Low power, Low Jitter Ring Oscillator Using 50nm CMOS Technology
Full Text(PDF, )  PP.236-240  
Nidhi Thakur
Voltage Controlled Oscillator (VCO), power dissipation, jitter, tuning range, phase locked loop (PLL)
A modified ring oscillator presented in this paper. The voltage control oscillator is designed and simulated in 50nm CMOS technology. The frequency of oscillation of the VCO is 2.6GHz with 0.064 mW power dissipation and the center drain current of 64uA is used. Tuning range is of 72% and the jitter is of 39.8pS.
[1] Mike Shuo-Wei Chen et al, “A Calibration-Free 800MHz Fractional-N Digital PLL with Embedded TDC”, ISSCC, February 2010.

[2] Mostafa Savedi Oskooei, AliAfzali-Kusha, S.M Atarodi. “A High-Speed and Low-Power Voltage Controlled Oscillator in 0.18-um CMOS Process”, IEEE Journal of Solid-State Circuits,pp.933-936, 2007.

[3] Neda Nouri and Shahriar Mirabbasi, “A900MHZ- 2GHZ LOW-SWING LOW-POWER 0.18µM CMOS PLL’’, IEEE CCECE/CCGEI, Saskatoon, 0-7803- 8886-0, pp.1558-1561, May 2005.

[4] Lizhong Sun and Tadeusz A. Kwasniewski, “A 1.25-GHz 0.35-um Monolithic CMOS PLL Based on a Multiphase Ring Oscillator”, IEEE Journal of SolidState Circuits,pp.910-916, VOL. 36, JUNE 2001.

[5] M.Vamshi Krishna, J.Xie, M.A.Do, C.C.Boon, K.S.Yeo and Aaron, A 1.8-V 3.6-mW 2.4-GHz Fully integrated CMOS Frequency Synthesizer for IEEE 802.15.4, 18th IEEE/IFIP International Conference on VLSI and System-on-Chip ,978-1-4244-6471, pp.387- 391, May 2010.

[6] Mehdi Ayat ,Behnam Babaei , Reza Ebrahimi Atani , Sattar Mirzakuchaki and Babak Zamanlooy, “Design of A 100MHz - 1.66GHz, 0.13µm CMOS Phase Locked Loop”, International Conference on Electronic Devices, Systems and Applications , 978-1- 4244-6632-0, pp.154-158,2010.

[7] S. J. Lee, B. Kim, and K. Lee, “A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme,” IEEE Journal of Solid-State Circuits, pp. 289–291, vol. 32, Feb-1997.

[8] C. H. Park and B. Kim, “A Low-Noise 900 MHz VCO in 0.6 µm CMOS,” IEEE Journal of Solid State Circuits, pp. 586 – 591, 1999.

[9] Ali Hajimiri, Sotirios Limotyrakis, and Thomas H. Lee, “Jitter and Phase Noise in Ring Oscillators”, IEEE Journal of Solid-State Circuits, 0018–9200/99, pp.790-804,VOL. 34, JUNE 1999.

[10]B. Razavi, “Design of Integrated Circuits for Optical Communications”, McGraw-Hill, New York, 2003.

[11] Ashish Raman and R. K. Sarin , “0.18-µm Low Power CMOS Ring Oscillator for Radio Frequency Applications”, International Journal of Computer Theory and Engineering, pp.770-774, Vol. 3, December 2011.

Untitled Page