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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 2    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 2,February 2012
Mechanism for Enhancing the Overall Performance of Multicore Processors
Full Text(PDF, )  PP.448-452  
Author(s)
Pankaj Rakheja, Charu Rana, Mandeep Singh Narula
KEYWORDS
Cache, checker, Thread
ABSTRACT
Multicore architectures are focused on improving the performance of the processor however their performance depends on the thread level parallelism of the application program which is difficult to extract and the design and production of multicore architectures is through a unreliable fabrication technology which imposes significant barriers to lifelong reliable operation of chip as they are vulnerable to defects and disturbances. In this paper we are proposing a mechanism to enhance overall performance of the multicore processors by adopting multiple cache cores and check cores with improvement in software managed L1 cache of computation core and algorithm implemented there to access right cache core to reduce cache miss and memory access frequency and to isolate it at right instant to prevent degradation in performance in case of L2 cache miss in cache core. We have designed a mechanism which will try to eliminate the defects in redundant as well as non redundant logic structures in the core for enhancing its performance and efficiency. We are stressing on thread scheduling, thread swapping and core salvaging at micro architectural level that is at the basic gate levels in the core which enhance overall performance and efficiency of the processor which can be aided by Intel quickpath interconnect technology and frequency scheduling that can reduce power consumption, speed up as well as optimize the core to core communication.
References
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