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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 2    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 2,February 2012
VLSI Design of Low Power Booth Multiplie
Full Text(PDF, )  PP.421-423  
Nishat Bano
Booth multiplier, Low power, modified booth multiplier, VHDL
This paper proposes the design and implementation of Booth multiplier using VHDL. This compares the power consumption and delay of radix 2 and modified radix 4 Booth multipliers. Experimental results demonstrate that the modified radix 4 Booth multiplier has 22.9% power reduction than the conventional radix 2 Booth Multiplier
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