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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 2    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 2,February 2012
VLSI Design of Low Power Booth Multiplie
Full Text(PDF, )  PP.421-423  
Author(s)
Nishat Bano
KEYWORDS
Booth multiplier, Low power, modified booth multiplier, VHDL
ABSTRACT
This paper proposes the design and implementation of Booth multiplier using VHDL. This compares the power consumption and delay of radix 2 and modified radix 4 Booth multipliers. Experimental results demonstrate that the modified radix 4 Booth multiplier has 22.9% power reduction than the conventional radix 2 Booth Multiplier
References
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[4] Abu-Khater, Bellaouar, and M. I. Elmasry, “Circuit Techniques for CMOS Low-Power High-Performance Multipliers”, IEEE Journal of solid-state circuits, volume 31, no. 10, October, 1996.

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[7] M. 0. Lakshmanan, Alauddin Mohd Ali, "High Performance Parallel Multiplier Using Wallace-Booth Algorithm," IEEE International Conference on Semiconductor Electronics, pp. 433-436, 2002.

[8] Oscal T. C. Chen, et.al, “Minimization of switching activities of partial products for designing low power multipliers”, IEEE Trans. VLSI systems, pp. 418-433, vol. 11, no. 3, June 2003.

[9] K.H. Tsoi, P.H.W. Leong, "Mullet - a parallel multiplier generator," fpl, pp.691-694, International Conference on Field Programmable Logic and Applications, 2005.

[10] S. K.Mangal and R. M. Badghare, “FPGA Implementation of Low Power Parallel Multiplier”, 20th International Conference on VLSI Design, IEEE, 2007

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