IJSER Home >> Journal >> IJSER
International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 1    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 1,January 2012
Reconfigurable Embedded Multiprocessor Architecture with ARISE interface using FPGA
Full Text(PDF, )  PP.76-80  
Author(s)
M. Abragam Siyon Sing, K. Vidya
KEYWORDS
ARISE Interface, VLIW Processor, FPGA, Wrapper.
ABSTRACT
Modern Embedded multiprocessor design presents challenges and opportunities that stem from task coarse granularity and the large number of inputs and outputs for each task. They are complex systems that often require years to design and verify. A significant factor is that engineers must allocate a disproportionate share of their effort to ensure that modern FPGA chips architecture behave correctly. Therefore, in order to reduce the complexity in design and verification, a new architecture is proposed which is implemented using FPGA. In this, the Embedded Processors are integrated with the shared memory system, synthesized that this system on an FPGA environment and ARISE interface is used to extent the processor and this interface is used once. Then, an arbitrary number of processors can be attached, via the interface, which can be a reconfigurable unit. Using this interface, more number of processor cores can be attached and bit to bit conversions can also be possible from one processor to another processor, that is, asymmetric processors can be built.
References
[1] Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading. J. lo, S. Eggers, J. Emer, H. Levy, R. Sstamm, and D. Tullsen.

[2] Multiprocessor System on chip Technology, Wayne Wolf.

[3] Design of a Branch Prediction Unit of a Microprocessor Based on Superscalar Architecture using VLSI, Dr. Mrs. Sulabha S. Apte, Ms. Priya P. Ravale, Solapur University.

[4] A reactive multiprocessor architecture for heterogeneous embedded systems, Zoran Salcic, Dong Hui, Partha S. Roop, Morteza BiglariAbhari.

[5] A Single-Path Chip-Multiprocessor System, Martin Schoeberl, Peter Puschner, and Raimund Kirner.

[6] A Complexity-Effective Architecture for Accelerating Full-System Multiprocessor Simulations Using FPGAs, Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai.

[7] R. Wittig and P. Chow, “OneChip: An FPGA processor with reconfigurable logic,” in Proc. IEEE Symp. FPGAs Custom Comput. Mach., 1996, pp. 126–135.

[8] F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, “Synthesis of custom processors based on extensible platforms,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. (ICCAD), 2002, pp. 641– 648.

[9] N. Vassiliadis, N. Kavvadias, G. Theodoridis, and S. Nikolaidis, “A RISC architecture extended by an efficient tightly coupled reconfigurable unit,” Int. J. Electron., vol. 93, no. 6, pp. 421–438, Jun. 2006.

[10] A. Lodi, M. Toma, F. Campi, A. Cappelli, R. Canegallo, and R. Guerrieri, “A VLIW processor with reconfigurable instruction set for embedded applications,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1876–1886, Nov. 2003.

[11] Farayadon Karim, Alain Mellan, Anh Nguyen, Utku Aydonat, and Tarek S. Abdelrahman. A Multi-Level Computing Architecture for Embedded Multimedia Applications. IEEE Micro, 24(3):55–56, 2004.

[12] H. Peter Hofstee. Power Efficient Processor Architecture and The Cell Processor. In HPCA ’05: Proceedings of the 11th International Symposium on High-Performance Computer Architecture, pages 258–262, Washington, DC, USA, 2005. IEEE Computer Society.

[13] J. Scott, L. Lee, J. Arends, and B. Moyer, “Designing the low-power M*CORE architecture,” in Proc. Int. Symp. Comput. Arch. Power Driven Microarch. Workshop, 1998, pp. 145–150.

[14] N. Vassiliadis, G. Theodoridis, and S. Nikolaidis, “Exploring opportunities to improve the performance of a reconfigurable instruction set processor,” Int. J. Electron., vol. 94, no. 5, pp. 481– 500, 2007.

[15] S. Hauck, T. W. Fry,M.M. Hosler, and J. P. Kao, “The chimaera reconfigurable functional unit,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 2, pp. 206–217, Feb. 2004.

[16] N. Vassiliadis, N. Kavvadias, G. Theodoridis, and S. Nikolaidis, “A RISC architecture extended by an efficient tightly coupled reconfigurable unit,” Int. J. Electron., vol. 93, no. 6, pp. 421–438, Jun. 2006.

[17] H. Singh, M.-H. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, and E. M. C. Filho, “MorphoSys: An integrated reconfigurable system for dataparalleland computation-intensive applications,” IEEE Trans. Computers, vol. 49, no. 5, pp. 465–481, May 2000.

[18] T. Miyamori and K. Olukotun, “REMARC: Reconfigurable multimedia array coprocessor,” in Proc. ACM/SIGDA 6th Int. Symp. Field Program. Gate Arrays (FPGA), 1998, p. 261.

[19] N. Clark, J. Blome, M. Chu, S. Mahlke, S. Biles, and K. Flautner, “An architecture framework for transparent instruction set customization in embedded processors,” in Proc. 32nd Annu. Int. Symp. Comput. Arch. (ISCA), 2005, pp. 272–283.

Untitled Page