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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 9    
Website: http://www.ijser.org
scirp IJSER >> Volume 2, Issue 9, September 2011
Comparison of CMOS and Adiabatic Full Adder Circuits
Full Text(PDF, 3000)  PP.  
Author(s)
Y.Sunil Gavaskar Reddy, V.V.G.S.Rajendra Prasad
KEYWORDS
Low-power, adiabatic logic, Full adder, CMOS, Pass transistor logic, Positive feed back adiabatic logic, Transmission gate
ABSTRACT
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count in 0.18um technology.
References
[1] W.C. Athas, L. Svensson, J.G. Koller et ,N.Tzartzanis and E.Y.Chou: “Low-power Digital Systems Bared on Adiabatic-switching Principles”. IEEE Transactions on VLSI Systems. Vol. 2, No. 4, pp. 398-407 December. 1994.

[2] A. Chandrakasan, S. Sheng and R. Brodersen, “Low-power CMOS digital design,” IEEE Journal of Solid State Circuits, Vol. 27, No 4, pp. 473-484, April 1992.

[3] N. Zhuang and H.Wu , “A New Design of the CMOS Full Adder,” IEEE Journal of Solid-state Circuits, Vol. 27,No. 5, pp 840-844,May 1992.

[4] S.Kang and Y.Leblebici, CMOS Digital Integrated Circuits - Analysis and Design, Reading chapter 6, McGraw-Hill, 2003.

[5] R K. Navi, Md.Reza Saatchi and O.Daei, “A High-Speed Hybrid Full Adder,” European Journal of Scientific Research,Vol 26 No.1,pp 29-33,January 2009.

[6] D. Sourdis, C. Piguet and C. Goutis, “ Designing CMOS Circuits for Low Power, European Low-Power Initiative for Electronic System Design”, Reading pp 71-96, Kluwer Academic Publishers, 2002.

[7] D. Soudris, V. Pavlidis and A. Thanailakis, “Designing Low-Power Energy Recovery Adders Based On Pass Transistor Logic,” IEEE 2001.

[8] R. Shalem, E. John and L.K. John, “A Novel Low Power Energy Recovery Full Adder Cell”publisher details unknown

[9] A.G.Dickinson and J.S.Denker, ""Adiabatic Dynamic Logic,"" IEEE Journal of Solid-state Circuits, Vol. 30 No.3, pp 311-315,March 1995.

[10] M.Alioto and G.Palumbo, “Power Estimation in Adiabatic Circuits: A Simple and Accurate Model”, IEEE Trans on VLSI Systems, VOL. 9, NO. 5, pp 608-615 October 2001.

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