IJSER Home >> Journal >> IJSER
International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 9    
Website: http://www.ijser.org
scirp IJSER >> Volume 2, Issue 9, September 2011
Design of Control unit for Low Power ALU Using Reversible Logic
Full Text(PDF, 3000)  PP.  
Ravish Aradhya H V, Praveen Kumar B V, Muralidhara K N
Fredkin Gate, Garbage output, Low Power, Power Optimization, Quantum Cost, Reversible control Unit, Reversible Logic.
Technology advances in VLSI designs offer exponentially shrinking device dimensions and exponentially growing circuit complexities. However, device scaling is critically limited by the power dissipation; demanding for better power optimizations methods. Reversible Logic is becoming more and more prominent special optimization technique having its applications in Low Power CMOS designs, Quantum Computing and Nanotechnology. ALU is a fundamental building block of a central processing unit (CPU) in any computing system; reversible arithmetic unit has a high power optimization on the offer. By using suitable control logic to one of the input variables of parallel adder, various arithmetic operations can be realized. In this paper, as a part of ALU design, a Reversible low power control unit for arithmetic operations is proposed. In our design, the full Adders are realized using synthesizable, low quantum cost, low garbage output Peres gates. In this paper data transfer, addition, subtraction, increment, decrement and many other Arithmetic operations are realized using reversible gates
[1]. C.H. Bennett , “Logical Reversibility of Computation”, IBM Journal of Research and Development, pp. 525-532, November 1973

[2]. R. Landauer, “Irreversibility and Heat Generation in the Computational Process”, IBM Journal of Research and Development, 5, pp. 183-191, 1961

[3]. C.H. Bennett, (1998) ""Notes on the History of Reversible Computation"", IBM Journal of Research and Development, vol. 32, pp. 16-23.

[4]. Anantha P. Chandrakasan, Samuel Sheng, and Robert W. Brodersen,” Low-Power CMOS Digital Design”, IEEE journal of Solid –State circuits.Vol.27,No. 4, April 1992 .

[5]. Yvan Van Rentergem and Alexis De Vos, (2005) “Optimal Design of a Reversible Full Adder”, International Journal of Unconventional Computing, vol. 1, pp. 339 – 355.

[6]. Majid Mohammadi, Mohammad Eshghi, Majid Haghparast and Abbas Bahrololoom, (2008) “Design and Optimization of Reversible BCD Adder/Subtractor Circuit for Quantum and Nanotechnology Based Systems”, World Applied Sciences Journal, vol. 4, no. 6, pp. 787-792.

[7]. Md. Saiful Islam, Muhammad Mahbubur Rahman, Zerina begum, and Mohd. Zulfiquar Hafiz “ Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry- Skip Adders”, MASAUM Journal of Basic and Applied Sciences, Vol. 1, No. 3, October 2009

[8]. Bart Desoete, Alexis De Vos “A reversible carry-look-ahead adder using control gates”, Science direct, INTEGRATION, the VLSI journal 33 (2002) 89–104.

[9]. Saiful Islam and Rafiqul Islam “Minimization of Reversible Adder circuits”, Asian Journal of Information Technology 4(12) 1146-1151, 2005.

[10]. Rangaraju H G et al,”Low Power Reversible Parallel Binary Adder/Subtractor”, International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010.

[11]. Himanshu Thapliyal and M B Srinivas, “Novel Design and Reversible Logic Synthesis of Multiplexer Based Full Adder and Multipliers”, Forty Eight Midwest Symposium on Circuits and Systems, vol. 2, pp. 1593 – 20061596.

[12]. Yingtao Jiang, Abdulkarim Al-Sheraidah, Yuke Wang, Edwin Sha, and Jin-Gyun Chung, ”A Novel Multiplexer-Based Low-Power Full Adder”, IEEE Transactions on circuits and systems -II: express briefs,vol. 51,No. 7 July 2004

[13]. Dmitri Maslov and Gerhard W. Dueck,” Reversible Cascades With Minimal Garbage” , IEEE Transaction on computer-aided design of integrated circuits and systems, vol. 23, No. 11, November 2004.

[14]. Alberto Nannarelli and Tomás Lang,” Low-Power Divider”, IEEE Transaction on computers, vol.. 48, No. 1, January 1999

[15]. Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, and John P. Hayes,” Synthesis of Reversible Logic Circuits”, IEEE Transaction on computer-aided design of integrated circuits and systems, vol. 22, No. 6, June 2003

[16]. William C. Athas, Lars “J” ,Svensson, Jeffrey G. koller, Nestoras Tzartzanis, and Eric Ying – Chin Chou,”Low-power Digital Systems based on Adiabatic-Switching principle”, IEEE Transactions on VLSI systems, Vol. 2, No. 4, December 1994.

[17]. Rekha K James, Shahana T K, K Poulose Jacob, and Sreela Sasi, “A New Look at Reversible Logic Implementation of Decimal Adder”, The International Symposium on System-On-Chip, 2007.

[18]. Lihui Ni, Zhijin Guan, and Wenying Zhu, “A General Method of Constructing the Reversible Full-Adder”, Third International Symposium on Intelligent Information Technology and Security Informatics, pp.109-113, 2010.

[19]. T Toffoli, “Reversible Computing”, Technical Memo MIT/LCS/TM-151, MIT Lab for Computer Science, 1980.

[20]. Hasan, H.B., R. Islam, A.R. chowdhury and S.M.A chowdhury,”Reversible logic synthesis for minimization of full adder circuit”, Euro micro symposium on digital system design, Belek Antalya, Turkey, PP: 50-54, 2003.

[21]. Perkowski M., L. Jozwiak, P. Kerntopf, A. Misohchenko and A. Al-Rabadi el. al., “A general decomposition for reversible logic” In: 5th Intl. Red-Mullar workshop, PP:119-138, 2001.

[22]. M. Morris Mono “Digital Logic and Computer Design”, Prentice-Hall of India, 2005.

[23]. J.M. Rabaey and M. Pedram, “Low Power Design Methodologies,” Kluwer Academic Publisher, 1997.

[24]. Azad khan, M.H., “Design of full adder with Reversible gates”. 5th ICCIT, East West University. PP: 515-519, 2002.

[25]. Bruce, J.W., M.A. Thornton, L. shivakuamaraiah, P.S. kokate and X. Li, “Efficient adder circuits based on a conservative reversible logic gate”, IEEE computer society Annual symposium on VLSI, Pittsburgh, Pennsylvania, and pp: 83-88, 2000.

Untitled Page