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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 10    
Website: http://www.ijser.org
scirp IJSER >> Volume 2, Issue 10, October 2011 Edition
Fault Modeling of Sequential Circuits at Register Transfer Level
Full Text(PDF, 3000)  PP.  
Author(s)
Suma M.S,K.S.Gurumurthy
KEYWORDS
fault coverage,fault list,fault models,fault simulation,RTL,stuck-at fault,test patterns
ABSTRACT
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tougher. As of now fault models are used to test digital circuits at the gate level or below that level. By using fault models at the lower levels, testing becomes cumbersome and will lead to delays in the design cycle. Thus there is a need to look for a new approach of testing the circuits at higher levels to speed up the design cycle. This paper proposes on Register Transfer Level (RTL) modeling for digital circuits and computing the fault coverage. The result obtained through this work establishes that the fault coverage with the RTL fault model is comparable to the gate level fault coverage.
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