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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 11    
Website: http://www.ijser.org
scirp IJSER >> Volume 2, Issue 11, November 2011
Design of High Gain Folded-cascode Operational Amplifier Using 1.25 µM CMOS Technology
Full Text(PDF, 3000)  PP.  
Author(s)
Er. Rajni Nagal
KEYWORDS
Operational amplifier, complementary metal-oxide semiconductor, common-mode range, input common-mode range, power-supply rejection ratio
ABSTRACT
This paper presents a design of the Folded-cascode operational amplifier using 1.25µm CMOS technology, which leads to high gain as compared to a normal cascode circuit. The simulation of the cascode and folded cascode circuits is done using TSPICE simulation tool and the LEVEL-2, 1.25 µm parameters are used. A complete analysis of the circuit is presented in this paper which shows how this circuit leads to a high gain and resistance at output. A comparison between the cascode and Folded-Cascode op amps is described. We have also described their simulated and calculated results comparison individually. This paper provides a considerable insight into the overall operation and advantages of the folded-cascode circuit. This design overcomes some limitations and drawbacks of the various previously presented described architectures
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