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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 5    
Website: http://www.ijser.org
scirp IJSER >> Volume 2, Issue 5, May 2011 Edition
Implementation of RSA Cryptosystem Using Verilog
Full Text(PDF, 3000)  PP.  
Chiranth E, Chakravarthy H.V.A, Nagamohanareddy P, Umesh T.H, Chethan Kumar M
Cadence, Cryptosystem, Decryption, Encryption, Implementation, Key Generation, Modular Exponentiation, Modular Multiplication, RSA, Verilog.
The RSA system is widely employed and achieves good performance and high security. In this paper, we use Verilog to implement a 16-bit RSA block cipher system. The whole implementation includes three parts: key generation, encryption and decryption process. The key generation stage aims to generate a pair of public key and private key, and then the private key will be distributed to receiver according to certain key distribution schemes. Data security is achieved after the 64-bit input data are block encrypted by RSA public key. The cipher text can be decrypted at receiver side by RSA secret key. These are simulated in NC LAUNCH and hardware is synthesized using RTL Compiler of CADENCE. Netlist generated from RTL Compiler will be used to generate IC.
[1] R.L.Rivest, A.Shamir, and L. Adleman, “A Method for Obtaining Digital Signatures and Public-Key Cryptosystems”, Communications of the ACM 21 (1978)

[2] Behrouz A.Forouzan, “Cryptography and Network Security”, Tata McGraw Hill, Special Indian Edition 2007.

[3] William Stallings, “Cryptography and Network Security”, Prentice-Hall of India private limited, Third Edition 2004.

[4] Neal Koblitz, “A Course in Number Theory and Cryptography”, Springer, Second Edition 2000.

[5] Implementing the Rivest, Shamir, Adleman cryptographic algorithm on the Motorola 56300 family of digital signal processors.


[6] Modular Arithmetic for RSA Cryptography.


[7] RSA Encryption


[8] Implementing a 1024-bit RSA on FPGA.

[Courtesy:http://www.arl.wustl.edu/~jl1/education/cs502/course_p roject.htm].

[9] Ridha Ghayoula, ElAmjed Hajlaoui, Talel Korkobi, Mbarek Traii, Hichem Trabelsi, “FPGA Implementation of RSA Cryptosystem”, International Journal of Engineering and Applied Sciences 2:3 2006.

[10] Tzong-Sun Wu, Han-Yu Lin,” Secure Convertible Authenticated Encryption Scheme Based on RSA”, Informatica 33 (2009) 481-486.

[11] Guilherme Perin, Daniel GomesMesquita, and Jo˜ao BaptistaMartins, “MontgomeryModularMultiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation”, Hindawi Publishing Corporation International Journal of Reconfigurable Computing Volume 2011.

[12] Muhammad I. Ibrahimy, Mamun B.I. Reaz, Khandaker Asaduzzaman and Sazzad Hussain, “FPGA Implementation of RSA Encryption Engine with Flexible Key Size”, International Journal of Communications.

[13] Chung-Hsien Wu, Jin-Hua Hong and Cheng-Wen Wu, “VLSI Design of RSA Cryptosystem Based on the Chinese Remainder Theorem”, Journal of Information Science and Engineering 17, 967-980 (2001).

[14] Md. Ali-Al-Mamun, Mohammad Motaharul Islam, S.M. Mashihure Romman and A.H. Salah Uddin Ahmad, “ Performance Evaluation of Several Efficient RSA Variants”, IJCSNS International Journal of Computer Science and Network Security, VOL.8 No.7, July 2008

[15] Ramzi A. Haraty, N. El-Kassar and Bilal Shibaro, “A Comparative Study of RSA Based Digital Signature Algorithms”, Journal of Mathematics and Statistics 2 (1): 354-359, 2006.

[16] Yi-Shiung Yeh, Ting-Yu Huang, Han-Yu Lin and Yu-Hao Chang, “A Study on Parallel RSA Factorization”, Journal of Computers, vol. 4, no. 2, February 2009.

[17] D. Boneh and H. Shacham, “Fast Variants of RSA”, CryptoBytes, Vol. 5, No. 1, pp. 1-9, 2002.

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