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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 5    
Website: http://www.ijser.org
scirp IJSER >> Volume 2, Issue 5, May 2011 Edition
Speedy Deconvolution using Vedic Mathematics
Full Text(PDF, 3000)  PP.  
Author(s)
Rashmi K. Lomte, Prof.Bhaskar P.C
KEYWORDS
Deconvolution, Non-Restoring algorithm, Urdhva Tiryagbhyam
ABSTRACT
Deconvolution is a computationally intensive digital signal processing (DSP) function widely used in applications such as imaging, wireless communication, seismology. In this paper deconvolution of two finite length sequences (NXM), is implemented using direct method to reduce deconvolution processing time. Vedic multiplier is used to achieve high speed. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. For division operation non-restoring algorithm is modified and used. The efficiency of the proposed convolution circuit is tested by embedding it on Spartan 3E FPGA. Simulation shows that ,the circuit has a delay of 79.595 ns from input to output using 90nm process library. It also provides the necessary modularity, expandability, and regularity to form different deconvolutions for any number of bits.
References
[1] John W. Pierre, “A Novel Method for Calculating the Convolution Sum of Two Finite Length Sequences”, IEEE transaction on education, VOL.39, NO. 1, 1996.

[2] Khader Mohammad, Sos Agaian, “Efficient FPGA implementation of convolution”, Proceedings of the 2009 IEEE International Conference on Systems, Man, and Cybernetics,San Antonio, TX, USA - October 2009.

[3] Koren,I. Computer Arithemetic Algorithms,Prentice-Hall Inc(1993)

[4] Hwang,K. Computer Arithmethmetic Principles,Arichitecture,and design,John Wiley & Sons.

[5] Ramesh Pushpangadan, Vineeth Sukumaran, Rino Innocent, Dinesh Sasikumar, Vaisak Sundarv, “High Speed Vedic Multiplier for Digital Signal Processors” IETE, VOL.55,page 282-286 118

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