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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 3    
Website: http://www.ijser.org
scirp IJSER >> Volume 2, Issue 3, March 2011 Edition
Design of HDLC Controller Using VHDL
Full Text(PDF, 3000)  PP.  
Author(s)
K.Sakthidasan, Mohammed Mahommed
KEYWORDS
HDLC, VHDL, Bit-level HDLC protocol operations.
ABSTRACT
In this paper, we explore a High-level Data link control published by International Standards Organization (ISO). HDLC is one of the most enduring and fundamental standards in Communications. HDLC is in itself a group of several protocols or rules for transmitting data between network points. The HDLC protocol also manages the flow or pace at which the data is sent. The data is organized into a unit called a frame. HDLC controllers are devices, which executes the HDLC protocol. Some of the key operations of the HDLC protocol implemented are handling bit oriented protocol structure and formatting data as per the packet switching protocol, it includes Transmitting and receiving the packet data serially and providing the data transparency through zero insertion and deletion. This controller generates and detects flags that indicate the HDLC status. The device contains a full duplex transceiver, with independent receive and transmit sections for bit-level HDLC protocol operations. The design is completely Synchronous, with separate clock inputs for receive and transmit allowing the two sections to operate asynchronously. These operations have been implemented using VHDL.
References
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