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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 3    
Website: http://www.ijser.org
scirp IJSER >> Volume 2, Issue 3, March 2011 Edition
Enhanced Mode of Extended Set of Target Fault Techniques in Single Stuck - At Fault for Fault Coverage in Benchmark Circuits
Full Text(PDF, 3000)  PP.  
P.Amutha, C.Arun Prasath
Benchmark circuits, fault simulation, stuck-at faults, test quality, unresolved faults.
The undetectable single stuck-at faults in full-scan benchmark circuits tends to cluster in certain areas. This implies that certain areas may remain uncovered by a test set for single stuck-at faults. The extension to the set of target faults aimed at providing a better coverage of the circuit in the presence of undetectable single stuck-at fault.. The extended set of target faults consists of double stuck-at faults that include an undetectable fault as one of their components. The other component is a detectable fault adjacent to the undetectable fault. Test sets that contain several different tests for each fault (n-detection test sets) are expected to increase the likelihood of detecting defects associated with the sites of target faults. This phenomenon is discerned from the gate level description of the circuit, and it is independent of layout parameters. In addition, the clustering is based on the gate level, and remains valid for any layout of the circuit. The fault simulation and test generation for the extended set of target faults is simulated using modelsim.
[1] S. M. Reddy, I. Pomeranz, and S. Kajihara, “Compact test sets for high defect coverage,” IEEE Trans. Comput.-Aided Design, vol. 16, no. 8, pp. 923–930, Aug. 1997. 2003, pp. 1031–1040..

[2] P. Goel and B. C. Rosales, “Test generation and dynamic compaction of tests,” in Proc. Test Conf., 1979, pp. 189–192.

[3] S. Kajihara, T. Sumioka, and K. Kinoshita, “Test generation for multiple faults based on parallel vector pair analysis,” in Proc. Int. Conf. Comput.- Aided Design, 1993, pp.

[4] J.-S. Chang and C.-S. Lin, “Test set compaction for combinational circuits,” in Proc. Asian Test Symp., 1992, pp. 20–25.

[5] H. Cox and J. Rajski, “A method of fault analysis for test generation and fault diagnosis,” IEEE Trans. Comput.-Aided Design, vol. 7, no. 7, pp. 813–833, Jul. 1988.

[6] S. Kajihara, I. Pomeranz, K. Kinoshita, and S. M. Reddy, “Costeffective generation of minimal test sets for stuck-at faults in combinational logic circuits,” IEEE Trans. Comput.-Aided Design, vol. 14, no. 12, pp. 1496– 1504, Dec. 1995.

[7] I. Hamazaoglu and J. H. Patel, “Test set compaction algorithms for combinational circuits,” in Proc. Int. Conf. Comput.-Aided Design, 1998,

[8] S. C. Ma, P. Franco, and E. J. McCluskey, “An experimental chip to evaluate test techniques experiment results,” in Proc. Int. Test Conf., 1995, pp. 663–672.

[9] M. Abramovici, M. A. Breuer, and A. D. Friedman, “Testing for single stuck faults,” Digital Systems Testing and Testable Design. Piscataway, NJ: IEEE, 1995, ch. 6, pp. 181–281...

[10] H. Tang, G. Chen, S. M. Reddy, C. Wang, J. Rajski, and I. Pomeranz, “Defect aware test patterns,” in Proc. Design Autom. Test Eur. Conf., 2005, pp. 450–455.

[11] I. Pomeranz and S. M. Reddy, “Forming N-detection test sets without test generation,” in Proc. ACM Trans. Design Autom., vol. 12. Apr. 2007, pp. 1–18.

[12] M. Abramovici and M. A. Breuer, “Multiple fault diagnosis in combinational circuits based on an effect-cause analysis,” IEEE Trans. Comput., vol. C-29, no. 6, pp. 451–460, Jun. 1980.

[13] Pomeranz, L. N. Reddy, and S. M. Reddy, “COMPACTEST: A method to generate compact test sets for combinational circuits,” in Proc. Int. Test Conf., Oct. 1991, pp. 194–203.

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