A High Performance and Low Power Hardware Architecture for H.264 Transform Coding
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Full Text(PDF, 3000) PP.
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Author(s) |
Jubli Kashyap,Virendra Kumar Yadav |
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KEYWORDS |
CMOS Technology, DCT, H.264, JVT, ITU-T, SoC, Quantization, YUV System, Zero Shift.
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ABSTRACT |
In the search for ever better and faster video compression standards H.264 was created. H.264 promises to be an excellent video format for use with a large range of applications and need for hardware acceleration of its very computationally intensive parts. To address this need, this paper proposes architecture for the discrete transform (DCT) and quantization blocks from H.264. The first set of architectures for the DCT and quantization were optimized for power, which resulted in transform and quantizer blocks that use 10.5623 mW Power. All of the designs were synthesized for Cadence BuildGate Synthesis CMOS technology, as well as the combined DCT and Quantization blocks went through comprehensive place and route flow.
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References |
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[1] I. Richardson, H.264 and MPEG-4 Video Compression,
Wiley, 2003
[2] Joint Video Team (JVT) of ITU-T VCEG and ISO/IEC
MPEG, Draft ITU-T Recommendation and Final Draft
International Standard of Joint Video Specification, ITUT
Rec. H.264 and ISO/IEC 14496-10 AVC, May 2003.
[3] ITU-T Rec. H.264 / ISO/IEC 11496-10, “Advanced
Video Coding”, Final Committee Draft, Document
JVTE022, September 2002
[4] INTRODUCTION TO DATA COMPRESSION 3RD EDITION BY
KHALID SAYOOD.
[5] H.264 AND MPEG-4 VIDEO COMPRESSION BY IAIN E G
Richardson.Published by John Wiley & Sons, September
2003.
[6] Multimedia Communications by Fred Halsal, Pearson
Educaton,2004.
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