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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 6    
Website: http://www.ijser.org
scirp IJSER >> Volume 2, Issue 6, June 2011 Edition
Low-Power 1-bit CMOS Full Adder Using Subthreshold Conduction Region
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Vishal Sharma, Sanjay Kumar
Low-Power, Subthreshold Conduction Region, Full Adder.
In balancing the trade-off between power, area and performance, numerous efforts have been done. However, not much study has been done at the two extreme ends of the design spectrum, namely the ultra low-power with acceptable performance at one end (the main concern of this paper), and high performance with power within limit at the other. This paper is based on the exclusive use of subthreshold conduction currents to perform circuit operations, yielding a dramatic improvement in power consumption compared to traditional circuit design approaches. This improvement makes it feasible to design extreme low-power circuits with such an approach. The CMOS digital circuits for this work have been designed using standard TSMC 0.18 μm Technology.
[1] K. Granhaug and S. Aunet, “Six Subthreshold Full Adder Cells characterized in 90 nm CMOS technology” IEEE Design and Diagnostics of Electronic Circuits and Systems, pp.25-30, 2006.

[2] S. Hanson, B. Zhai, K. Bernstein, D. Blaauw, A. Bryant, L. Chang, K. K. Das, W. Haensch, E. J. Nowak and D. Sylvester, “Ultralow-voltage, minimum-energy CMOS,” IBM Journal of Research and Development, vol. 50, no. 4-5, pp. 469–490, 2006.

[3] V. Sharma and S. Kumar, “Design of Low-Power CMOS Cell Structures Using Subthresold Conduction Region” International Journal of Scientific and Engineering. Research, vol. 2, Feb 2011.

[4] A. P. Chandrakasan, S. Sheng and R. W. Brodersen, “Low Power CMOS Digital Design,” IEEE Journal of Solid-state Circuits, vol. 27, no. 4, pp. 473-484, April 1999.

[5] H. Soeleman, K. Roy and B. C. Paul, “Robust subthreshold logic for ultra low-power operation,” IEEE Trans.VLSI Syst., vol. 9, pp. 90-99, Feb. 2001.

[6] V. Moalemi and A. Afzali-Kusha, “Subthreshold 1-bit Full Adder Cells in 100 nm Technologies,” IEEE Computer Society Annual Symposium on VLSI, pp. 514-515, May 2007.

[7] K. Ragini and B. K. Madhavi, “Ultra Low Power Digital Logic Circuits in Subthreshold for Biomedical Applications,” Journal of Theoretical and Applied Information Technology, 2005.

[8] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer cmos circuits,” in Proceedings of IEEE, vol. 91, no. 2, pp. 305-327, 2003.

[9] A. Wang, B. H. Calhoun and A. P. Chandrakasan, Subthreshold Design For Ultra Low-Power Systems, Springer, USA, 2006.

[10] R. M. Swanson and J. D. Meindl, ""Ion-Implanted Complementary MOS Transistors in Low-Voltage Circuits,"" IEEE Journal of Solid-State Circuits, vol. 7, no. 2, pp. 146-153, April. 1972.

[11] S. M. Kang and Y Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, 3rd ed, McGraw Hill, 2004.

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