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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 7    
Website: http://www.ijser.org
scirp IJSER >> Volume 2, Issue 7, July 2011 Edition
Design and Performance Analysis of a 3GPP LTE/LTE-Advance Turbo Decoder using Software Reference Models
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Author(s)
Lohith Kumar H G, Manjunatha K N, Prof.Cyril Prasanna Raj P, Suma M S, C K Raju
KEYWORDS
3GPP LTE, Convolutional interleaver, MAP decoder, SOVA, Turbo decoder, VLSI ASIC.
ABSTRACT
This paper presents the design and development of an efficient VLSI architecture for 3GPP advanced Turbo decoder by utilizing the convolutional interleaver. The high-throughput 3GPP Advance Turbo code requires turbo decoder architecture. Interleaver is known to be the main obstacle to the decoder implementation and introduces latency, due to the collisions it introduces in accesses to memory. In this paper, we propose a lowcomplexity soft Input Soft Output (SISO) turbo decoder for memory architecture to enable the Turbo decoding that achieves minimum latency. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed Turbo decoder has been modeled using Simulink; various test cases are used to estimate the performances. The results are analyzed and achieved 50% reduction in computation time along with reduced BER (e-3).
References
[1] Evolved Universal Terrestrial Radio Access (EUTRA) and Evolved Universal Terrestrial Radio Access Network (EUTRAN), 3GPP TS 36.300.

[2] General UMTS Architecture, 3GPP TS 23.101 version 7.0.0, June 2007.

[3] S.Parkvall, E.Dahlman, A.Furuskar, Y.Jading, M.Olsson, S.Wanstedt, K. Zangi, “LTE-advanced- evolving LTE towards IMT advanced”, in: IEEE Vehicular Technology Conference, September2008,pp.1–5.

[4] Multiplexing and channel coding, 3GPP TS 36.212 version 8.4.0, September 2008.

[5] H. R. Sadjadpour, N. J. A. Sloane, M. Salehi, and G. Nebe, ‘Interleaver design for turbo codes’ IEEE Journal on Selected Areas in Communications, vol. 19, no 5, pp. 831- 837, 2001.

[6] R. D. Raut, Dr. K.D. Kulat “International Journal of Computer Applications”(0975 - 8887) Volume 1 – No. 24 ©2010

[7]Y. Sun, J.R. Cavallaro,” Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder”, Integration VLSI J. (2010), doi:10.1016/j.vlsi.2010.07.001

[8] B. K. Upadhyaya, S. K. Sanyal “ VHDL Modeling of Convolutional Interleaver- Deinterleaver for Efficient FPGA Implementation”, International Journal of Recent Trends in Engineering, Vol 2, No. 6, November 2009.

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