IJSER Home >> Journal >> IJSER
International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 5    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 5,May 2012
Low Leakage Nanoscaled Body on Insulator FinFET with Underlap
Full Text(PDF, )  PP.937-946  
Sarika Bukkawar, Nisha Sarwade
—BOI(Body over Insulator)FinFET,BOX(Buried Oxide) DIBL(Drain Induced Barrier Lowering) ,leakage current, short-channel effects (SCEs), silicon-on-insulator (SOI), subthreshold slope(S), underlap length (LUN ) .
In this paper a Body over Insulator(BOI) FinFET structure in which channel region insulated from body by buried oxide with undoped underlap is studied . An extensive simulation study and analysis of the effect of underlaps on BOI FinFET has been performed using the TCAD SILVACO (DevEDIT(3D), ATLAS). The simulations have revealed that the BOI FinFET structures with underlaps are more efficient than conventional BOI FinFET as undoped underlap region reduces DIBL, leakage current(IOFF) and improves ION/IOFF ratio. 
[1] Leland Chang, YANG-KYU Daewon,,Pushkar Ranade,Shiying Xiong,,Jeffery Bokor,Chenming Hu,and Tsu-Jaeking, ―Extremely Scaled Silicon Nano-CMOS Devices‖ proceedings of the IEEE Vol.91,No.11,Nov2003

[2] Edward J. Nowak, Ingo Aller, Thomas Ludwig, Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang, Kerry Bernstein, and Ruchir Puri, ―Turning Silicon On Its Edge‖ I EEE circuits & devices magazine Jan/Feb 2004,pp-20-31

[3] RONALD R. TROUTMAN , ―VLSI Limitations from Drain-induced Barrier Lowering‖ IEEE Solid –State Circuit Journal of Solid State Circuit Vol-SC-14, No. 2, April 1979 pp-383-390

[4] Mirko Poljaka, Vladimir Jovanovićb and Tomislav Suligoj, ―Technological constrains of bulk FinFET structure in comparison with SOI FinFET‖ ISDRS 2007, December 12-14, 2007

[5]S.L.Partridge,―Silicon-on-insulator technolog‖ IEE Proceedings , Vol. 133, Pt. I, No.3, JUNE 1986

[6] K. K. Young, ―Short-channel effects in fully depleted SOI MOSFETs,‖ IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 399–402, Feb. 1989.

[7] M. J. Kumar and A. A. Orouji, ―Investigation of a new modified source/ drain for diminished self-heating effects in nanoscale MOSFETs using computer simulation,‖ Phys. E, vol. 33, no. 1, pp. 134–138, Jun. 2006.

[8] C. Fiegna, Y. Yang, E. Sangiorgi, and A. G. O’Neill, ―Analysis of selfheating effects in ultrathin-body SOI MOSFETs by device simulation,‖ IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 233–244, Jan. 2008.

[9] J. Roig, D. Flores, M. Vellvehi, J. Rebollo, and J. Millan, ―Reduction of self-heating on SOIM devices,‖ Microelectron. Reliab., vol. 42, no. 1, pp. 61–66, Jan. 2002.

[10] Z. R. Song, Y. H. Yu, C. L. Li, S. C. Zou, F. M. Zhang, and X. Wang,―Tetrahedral amorphous-carbon thin films of silicon-on-insulator application,‖Appl. Phys. Lett., vol. 80, no. 5, pp. 743–747, Feb. 2002.

[11] Jia Liu, Zhijiong Luo, Haizhou Yin, Huilong Zhu, Hefei Wang, Feng Yuan, ―Low Leakage Bulk Silicon Substrate Based SDOI FINFETs‖ IEEE 978- 1-4244-5798- 2010

[12] Sajad A. Loan, S. Qureshi, andS. Sundar Kumar Iyer, ― A Novel PartialGround-Plane-Based MOSFET onSelective Buried Oxide: 2-D Simulation Study‖ IEEE Transactions on Electron Devices VOL. 57, NO. 3, MARCH 2010,pp 671-680

[13] Nihar R. Mohapatra, Madhav P. Desai and V. Ramgopal Rao, ―Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics‖ Proceedings of the 16thInternational Conference on VLSI Design (VLSI’03)

[14] G.C.-F. Yeap, S. Krishnan and Ming-Ren Lin,―Fringing-induced barrier lowering (FIBL) in sub-100nm MOSFETs with high-/(gate dielectrics‖ Electronics Letters 28th May 1998 Vol. 34 No. I 1pp-1150-1152

[15] Angada B. Sachid, C. R. Manoj, Dinesh K. Sharma, and V. Ramgopal Rao, ―Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization.‖ IEEE Electron Device letters , Vol. 29, No. 1, January 2008,pp-128-130

[16] Bing-Yue Tsui and Li-Feng Chin, ―A Comprehensive Study on the FIBL of Nanoscale MOSFETs‖ IEEE Transaction on Electron Devices Vol. 51, No. 10, October 2004,pp-1733-1735

[17] Gaurav Saini, Ashwani K Rana, Pankaj Kr. Pal, Sunil Jadav,―Leakage Behavior of Underlap FinFET Structure: A Simulation Study‖ Int’l Conf. on Computer & Communication Technology | ICCCT’10 |pp-302-305

[18] Angada B. Sachid, Roswald Francis, Maryam Shojaei Baghini, Dinesh K. Sharma, Karl-Heinz Bach, Reinhard Mahnkopf, V. Ramgopal Rao, ―Sub-20 nm Gate Length FinFET Design: Can High-κ Spacers Make a Difference?‖ [19]Vishal Trivedi, Jerry G. Fossum, and Murshed M.

Chowdhury,―Nanoscale FinFETs With Gate-Source/Drain Underlap‖ IEEE electron Devices, VOL. 52, NO. 1, JANUARY 2005,pp-56-62

[20]Nihar R. Mohapatra, Madhav P. Desai, Siva G. Narendra, andV. Ramgopal Rao,―The Effect of High-K Gate Dielectrics on Deep Submicrometer CMOS Device and Circuit Performance‖ IEEE Transaction on Electron Devices, VOL. 49, NO. 5, MAY 2002,pp-826-831

[21]Tamara Rudenko, Valeria Kilchytska, Nadine Collaert, S. De Gendt,,Rita Rooyackers, Malgorzhata Jurczak, and Denis Flandre―Specific Features of the Capacitance and Mobility Behaviors in FinFET Structures‖ Proceedings of ESSDERC, Grenoble, France, 2005,pp-85-88

[22]Silvaco,Atlas User’s Manual, chapter 13. California, USA.

[23] Ashfaqul Anwar, Imran Hossain’ ―Comparative Numerical Simulation of a Nanoscaled Body on Insulator FinFET‖ ,PROC. 27th INTERNATIONAL CONFERENCE ON MICROELECTRONICS(MIEL 2010), NIŠ, SERBIA, 16- 19 MAY, 2010 ,pp 413-416

Untitled Page