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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 5    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 5,May 2012
Mitigating Techniques to Reduce Sub-threshold Currents in Submicron MOSFETs[
Full Text(PDF, )  PP.823-828  
Author(s)
Akhil Ulhas Masurkar
KEYWORDS
Scaling, Nanometer, Leakage, sensitivity, mitigating, simulating, fabrication, SILVACO
ABSTRACT
Scaling transistors into the nano-meter regime has resulted in a dramatic increase in MOS leakage current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. Therefore it is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation techniques in nano-meter technologies by designing accurate models of short channel devices and simulating the same using the available standard CAD tools. This paper provides an overview of the mitigating techniques used during the fabrication of the MOSFET using SILVACO.
References
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