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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 5    
Website: http://www.ijser.org
scirp IJSER >> Volume 3,Issue 5,May 2012
Mixed signal IC (CP-PLL) Testing scheme using a novel approach
Full Text(PDF, )  PP.761-768  
Author(s)
Ashish Tiwari, Anil Kumar Sahu
KEYWORDS
Area overhead, BIST, CP-PLL, IC, fault coverage, Phase frequency detector, testing, VCO.
ABSTRACT
An effective novel approach for built in self test is proposed in this paper, which is useful in Mixed signal IC testing (here CP-PLL). The approach is useful in digital testing applications which can detect the fault in any of the block that is phase frequency detector, VCO, loop filter, or charge pump. The key advantage of this approach is that it uses all the existing elements for measuring and testing which reduces the area overhead for testing scheme. Restated, that the proposed architecture does not alter the analog blocks. Rather the proposed approach adds small circuits to PLL with slight modification for digital part. The testoutput generated is purely a digital output which certainly increases the realiability of the proposed BIST structure. A fault simulation result shows the charactericstics of the BIST structure that is high fault coverage of 98%. The implemtation is done using the Tanner, VHDL and waveforms are made using the T- Spice.
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