IJSER Home >> Journal >> IJSER
International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 12    
Website: http://www.ijser.org
scirp IJSER >> Volume 2, Issue 12, December 2011
Reduced Dynamic Power Shift And Add Multiplier Design
Full Text(PDF, 3000)  PP.  
K. Sreenivasa Rao, D. Rajesh Setty
Low power multiplier, add multiplier, low power ring counter, sources of switching activities, bidth width controller, multiplier register
Today every circuit has to face the power consumption issue for both portable devices aiming at large Battery life and high end circuits avoiding cooling packages and reliability issues those are too complex. It is generally accepted that during logic synthesis power tracks well with area. This means that a larger design will generally consume more power. In this paper a low power low area architecture for the shift and add multiplier is proposed. For getting the low power low area architecture, the modifications made to the conventional architecture consist of the reduction in switching activities of the major blocks of the Multiplier, which includes the reduction in switching activity of the adder and counter. This architecture avoids the shifting of the multiplier register. The simulation result for 16 bit multipliers shows that the proposed low power architecture lowers the total power consumption by 40.15% when compared to the conventional architecture. Also the reduction in power consumption increases with the increase in bit width.
[1] A.Chandrakasan and R. Brodersen, “Low Power CMOS Digital Design”, IEEE J. Solid State Circuits, Vol.27, no.4, pp 473-484, Apr 1992

[2] N.Y.Shen and O.T.C.Chen.""Low power multipliers by minimizing switching activities of partial products"" in Proc. IEEE Int.Symp.Circuits Syst., May 2002, Vol.4, pp 93-96.

[3] O.T.Chen, S.Wang and Y, W.Wu ""Minimization of switching activities of partial products for designing low power multipliers"" IEEE Trans. Very Large Scale Integer. (VLSI)Syst., Vol .11, No-3, pp418-433, June 2003

[4] B.Parhami Computer arithmetic algorithms and Hardware designs 1 st ed.Oxford U.K. Oxford Univ, Press 2000.

[5] K.H.Chen and Y.S.Chu, ""A low power multiplier with spurious power suppression technique”, IEEE Trans. Very Large Scale Integr. (VLSI)Syst., Vol.15, no-7, pp846-850, July 2007

[6] K.H.Chen K.C.Chao, J.I.Guo, J.S.Wang and Y.S.Chu. ""An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design"" in Proc.IEEE Int.Symp.Low Power Electron.Des. 2005 pp 155-160

[7] M.Mottaghi Dastjerdi, A.afzali Kusha, m.Pedram “BZFAD A Low Power Low Area Multiplier Based on Shift and Add Architecture “IEEE Trans. Very Large Scale Integr. (VLSI)Syst., Vol.17, no-2, pp302-306, Feb. 2009

[8] Ercegovac M.D. and Huang Z. (March 2006) “High performance low power left to right array multiplier design” IEEE Trans. Comput., Vol-54, no-2, pp 272-283.

[9] Chen K.H., Chen Y.M. and Chu Y.S. (May 2007) “A Versatile Multimedia functional Unit Design Using the Spurious Power suppression Technique” in Proc.IEEE Asian Solid State Circuits Conf., pp111-114.

Untitled Page