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International Journal of Scientific and Engineering Research
ISSN Online 2229-5518
ISSN Print: 2229-5518 12    
Website: http://www.ijser.org
scirp IJSER >> Volume 2, Issue 12, December 2011
Reduced Dynamic Power Shift And Add Multiplier Design
Full Text(PDF, 3000)  PP.  
Author(s)
K. Sreenivasa Rao, D. Rajesh Setty
KEYWORDS
Low power multiplier, add multiplier, low power ring counter, sources of switching activities, bidth width controller, multiplier register
ABSTRACT
Today every circuit has to face the power consumption issue for both portable devices aiming at large Battery life and high end circuits avoiding cooling packages and reliability issues those are too complex. It is generally accepted that during logic synthesis power tracks well with area. This means that a larger design will generally consume more power. In this paper a low power low area architecture for the shift and add multiplier is proposed. For getting the low power low area architecture, the modifications made to the conventional architecture consist of the reduction in switching activities of the major blocks of the Multiplier, which includes the reduction in switching activity of the adder and counter. This architecture avoids the shifting of the multiplier register. The simulation result for 16 bit multipliers shows that the proposed low power architecture lowers the total power consumption by 40.15% when compared to the conventional architecture. Also the reduction in power consumption increases with the increase in bit width.
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