The Study of ESD Robustness of Integrated Circuits with Standard TLP [ READ ]
M. Lally, M. Ahuja, B. Mehria
In this work the ESD performance of BCD technology will be investigated at circuit level. Different types of structures and the layout effect on ESD robustness will be addressed. The correlation between ESD robustness obtained with different test methods (HBM and TLP) will be also presented.
M. Lally, M. Ahuja, B. Mehria
In this work the ESD performance of BCD technology will be investigated at circuit level. Different types of structures and the layout effect on ESD robustness will be addressed. The correlation between ESD robustness obtained with different test methods (HBM and TLP) will be also presented.
