International Journal of Scientific & Engineering Research Volume 2, Issue 9, September-2011 1

ISSN 2229-5518

Implementation of Generic Algorithm Using VHDL

on FPGA

Prashant Sen *, Priyanka Pateriya **

problems, function optimal problems.

—————————— ——————————

In general, the step of GA operations consists of 6 main steps: population initialization, fitness calculation, selection, crossover, mutation and termination judgment, is shown in Fig.2. In the beginning, the initial population of a GA is generated random- ly. Then, the evaluation values of the fitness function for the individuals in the current population are calculated. And then, the 3 steps of GA operators: selection, crossover, and mutation are performed. Finally, the termination criterion is checked, and the whole GA procedure stops if the termination criterion is reached. Our design and develop hardware in the GA process conclude RNG operation, crossover operation, and mutation operation.

————————————————

**Department Of Computer Science & Engg.B.T.Institute Of Research & Technology Sagar M.P. India E-mail: *prashantsen@yahoo.com

***Department Of Electronics & Communication Engg.B.T.Institute Of*

Research & Technology Sagar M.P. India, E-mail: ppateriyaec@yahoo.co.in

In this paper, we have classified the chromosome encoding ac- cording to the most prefer are 3 types compose of: binary encod- ing, real-value encoding, and integer encoding, that can describe are as follow:

Crossover operation: Used in selection of the genes from parent chromosomes and creates a new issue. The simplest way how to

IJSER © 2011

International Journal of Scientific & Engineering Research Volume 2, Issue 8, August-2011 2

ISSN 2229-5518

do this is to choose randomly some crossover point and every- thing before this point copy from a first parent and then every- thing after a crossover point copy from the second parent.

Mutation operation: After crossover performed, mutation take place. This is to prevent falling all solutions in population into a local optimum of solved problem. Mutation changes randomly the new issue. Which, can switch a few randomly chosen bits from „1‟ to „0‟ or from „0‟ to „1‟. For example “[ 1 1 0 1 0 1 1 ] => [ 1

1 1 1 0 1 0 ]”

Crossover operation: All crossovers from binary encoding can be used.

Mutation operation: Adding a small number to selected values is added (or subtracted). For example “(6 2.86 4.11 5.47) => (6 2.73

4.22 5.47)”

Crossover operation: One-point crossover is selected, till this point the integer is copied from the first parent, then the second parent is scanned and if the number is not yet in the offspring it is added. For example “(1 2 3 4 5 6 7 8 9), (4 5 3 6 8 9 7 2 1) => (1 2 3 4

5 6 8 9 7)”

Mutation operation: Order changing, two numbers are selected

and exchanged. For example “(1 2 3 4 5 6 8 9 7) => (1 8 3 4 5 6 2 9

7)”

A basic idea in this work is to implement the hardware architec- tures of RNG ( random number generation), crossover, and muta- tion. Because the 3 architecture are depend on the encoding oper- ation. Difference encoding operation requires difference crossov- er and mutation. So, this hardware architecture design based on flexibility to the 3 types encoding for working together at a time. However the main drawbacks of hardware design are difference operation of crossover and mutation in each encoding. The main process of 3 hardware architecture are the users can choose any one of 3 type encoding according to the requirement of various GA applications, is shown in Fig 3.

III. PROPOSED HARDWARE ARCHITECTURE FOR GA

In this paper, we have design and develop the 3 hardware architecture of the GA process, that concluding: random num- ber generator module, crossover module, and mutation mod- ule, are as follow:

We have to take advantage of linear feedback shift register

(LFSR) for random number generated. The operation of LFSR

are generated by D flip-flop, is show in Fig. 4. And a first bit

(X0) to take XOR with a last-bit (Xn) represent feedback, that is repeat process many time. as following the equation (1).

X0(n +1) = Xn(n) + X0(n)…………………. (1)

When X0(n +1) represent as data bit 0 at clock time (n +1), X0(n) represent as data bit 0 at clock time (n), and Xn(n) represent as data bit n at clock time (n).

The crossover module is used to perform the crossover opera- tions on the two winner individuals, which are denoted A and B. The operator module offers, four crossover operations, in- cluding uniform, single-point, two-point, and cross-point. This crossover can use flexible to binary encoding, real-value en- coding, and integer encoding. Users can choose any one of them according to their needs. The output chromosomes, which are denote A' and B', are then sent to the following mu- tation module, is show in Fig. 5.

IJSER © 2011

International Journal of Scientific & Engineering Research Volume 2, Issue 8, August-2011 3

ISSN 2229-5518

The mutation module is used to avoid converging to the local optimization and instead locate the better solutions. A flexible mutation rate setting scheme is used. This mutation can use flexible to binary encoding, real-value encoding, and mutation encoding. User can easily choose an appropriate mutation rate according to their needs. In the design, the mutation operation is performed when the user-defined mutation rate exceeds the threshold, and it is also used to generate the new chromo- some. Finally, the generated chromosome is into the popula- tion initialization, is show in Fig. 6

for design and reduce a cost for hardware implementation.

The simulation of crossover module, is show in Fig. 8. After the

random number generated. The crossover operation are per-

formed. In this example simulation for the binary encoding and real-value encoding can used. The VHDL code have to design for

binary number = 8-bit, crossover point = 3 bit, integer n = 7. The simulation of mutation module, is shown in Fig. 9. This simula- tion is an example of binary encoding and integer encoding. The VHDL code design is one-point mutation, integer n = 7, for bi- nary number = 8 bit, and mutation point = 3 bit. The experimen- tal results, we have compare our design with, which the flexible to finding the minimum-maximum of the complex function. Which has only real-value encoding.

Fig 7 Simulation of RNG Module

The 3 groups problems, that is depend on the three types encod- ing have been experimental in this work. The group problems are as follow: Group#1, is combinatorial optimization problems, that compose of knapsack problem, minimum spanning tree problem, and set-covering problem. They have chromosome encoding to binary number. Group#2, is function optimal problems that is searching to max-min of the complex function, which has chro- mosome encoding as real value number. For example “find the maximum of a 1-d trigonometric function, and find the minimum of a 2-d Schubert function). Group#3, is path planning optimiza- tion problems This problem is about to find the optimal part from start point to final point. For example “find a optimal part of traveling salesman problem, and find a optimal part planning of a robot machine. The simulation result, we can used ModelSim program and VHDL code to design and synthesized. The simula- tion of RNG module is show in Fig. 7. The output can separate to three part: q1 represent binary output, q2 represent integer out- put, and q3 represent real-value output. The integer range -1 to

255, binary 8-bit, number of array equal to 36. For the VHDL code to design for RNG, we can used function in package

“std_logic_unsigned” is

conv_ integer (arg : std_logic_vector) return integer;

and converse from integer to “std_logic_vector” can used

function in package “std_logic_arith” is conv_std_logic_vector (arg : integer; size : integer) return std_logic_vector;

and take 2‟complement for conversion binary to real-number, and then conversion from real-number to integer respectively. So,

the advantage of RNG module in this work is not use much time

IJSER © 2011

International Journal of Scientific & Engineering Research Volume 2, Issue 8, August-2011 4

ISSN 2229-5518

The 3 architectures have been designed using VHDL and then it is synthesized and verified. For the simulations, we used the ModelSim program and implementation will be on FPGAs. The GA requires very intensive computations to perform op- timization. Hence, a dedicated VLSI implementation is neces- sary. All of most, a hardware GA requires very flexible to var- ious applications. We have proposed development of a flexible hardware core for GA.

References

1. T. Tatsuhiro, M. Yoshihiro, S. Naoki, Y. Keiichi, and I.

Minoru, “Flexiblen Implementation of Genetic Algo-

rithm on FPGAs”, IEEE Int.Conf., 2008.

2. P. Vipapun and K. Pinit, “A High-Speed Hardware of the Geneticn Algorithm for Combinatorial Optimiza- tion Problem”, in Proc.3rd IEEE Int. Conf. on Com- munication and Information Technology, vol. 2, Sep- tember 2003.

3. N. Shruthi and P. Carla, “Hardware Implementation of the Genetic Algorithm Modules for Intelligent Sys- tem”, IEEE Int. Conf., 2005.

4. F. Pradeep, S. Hariharan, K. Srinivas, K. Didier, S.

Adrian, Z. Ricardo, and R. Ramesham, “A Customiz-

able FPGA IP Core Implementation of a General Pur-

pose Genetic Algorithm Engine”, IEEE Int. Conf.,

2008.

5. J. Yutana and C. Prabhas, “Cellular Compact Genetic Algorithm for Evolvable Hardware”, IEEE Int. Pro. of ECTI-CON, 2008.

6. G. Xianyue, L. Hongyan, and W. Shufeng, “A Dynam- ic Byte Encoding Genetic Algorithm for Numerical Optimization”, IEEE Int. Conf. 3rd on Innovative Computing Information and Control(ICICIC‟08),

2008.

7. D. Yuan-Ming and W. Xuan-Yin, “Real-coded adap- tive genetic algorithm applied to PID parameter op- timization on a 6R manipulators”, IEEE Int. Conf. 4th on Natural Computation, 2008.

8. M. Mansouri, M. Aliyari Shoorehdeli, and M. Tesh- nehlab, “Integer GA for Mobile Robot Path Planning with using another GA as Repairing function”,IEEE Int. Conf. on Automation and Logistic, September

2008.

————————————————

*Prashant Sen B.E. (CSE), MTECH (IT),*

. E-mail: prashantsen@yahoo.com

Priyanka Pateriya B.E.(ECE) MTECH (pursuing), E-mail: ppateriyaec@yahoo.co.in

IJSER © 2011