International Journal of Scientific & Engineering Research Volume 2, Issue 10, Oct-2011 1

ISSN 2229-5518

Dynamic Response of Jospephson Resistive

Logic (RCJL) GATE

K.Srinivas and J. C. Biswas

—————————— ——————————

Two attractive features of SQUID devices for logic applications are isolation and serially connected fan-out. The isolation is provided by the transformer coupling between the SQUID and the input. The isolation is not perfect in the sense that a noise pulse (typically 5 percent) is fed back into the control line when the SQUID switches to the non-zero voltage. The other advantage is the serial fan- out capability by which the control lines of many load devices can be connected in series with a single output line. The main drawbacks of SQUID devices for logic application are relatively large device area and high sensitivity to stray magnetic fields. In SQUID 80% of the area is occupied by the transformer [1]. Further, the high sensitivity to stray magnetic field requires that the SQUID based logic circuits be well shielded from the stray magnetic fields.

The resistive logic gates such as JAWS (Josephson Auto- Weber System) [2], DCI (Direct Coupled Isolation) [3] and RCJL (Resistor Coupled Josephson Logic) [4] are chosen because the gate logic delay in this case would consist of the turn-on delay, switching delay and propagation delay, but not the crossing delay as in the case of magnetically coupled logic gates. Further, these resistive logic gates do not have a factor of limiting the size very seriously. So, the gate propagation delay can be made sufficiently small. Therefore, the small time constant of the Josephson junction can be directly attained to these gates.

It has been considered by the earlier workers [5] that the turn-on delay of a logic gate is the time taken for the logic gate to obtain 2% of the output current to the load. This consideration seems to be arbitrary.

Due to this fact, in the present paper we have made a

thorough investigation of the resistive logic gates. Our

concept of turn-on delay [6] has been introduced which will

be able to remove the confusion in critically ascertaining the

COMMUNICATION ENGINEERING, INDIAN INSTITUTE OF TECHNOLOGY , KHARAGPUR-721302 INDIA.

The curcuit configuration and the threshold curve for the RCJL gate are shown in Fig.l. The junctions J1, J2 and J3 have critical currents Io, 3/2 Io, and 3/2 Io, and junction capacitances of Cj, 3/2 Cj, and 3/2 Cj, respectively. The resistor R2, R3 and R4 have the same values of the resistance r' and the resistance of R1 is r. The RCJL gate is biased in the superconducting state by the injection of the input current Iin. The junction J2 plays a role of the current-summing junction in this gate. The operation of the RCJL gate is as follows:

Intially the gate current Ig splits into Igl and I g2 in the inverse ratio of resistors r2 and r3. When the input current Iin (Ic) is applied at the node C, the Iin goes through the junction J1 and is injected into the junction J2. The junction J2 subsequently switches from the superconducting state to the resistive state. A fraction of the Josephson current having shown in J2, swings over the junction J3 through r2, r3, r4, and causes J3 to switch. Consequently, the gate current Ig is steered towards the junction J1, and J1 switching results. After J1 switching, Ig is steered into the load Rl and I in is teriminated through Rl. Gate switching with input-output isolation is completed. In the RCJL gate, total Iin current contributes to initialization of the switching sequence, while only a fraction of Ig contributes to it. This results in a high input sensitivity.

According to Fig.2, the current equations at each statge of

the RCJL gate can be written as: Ig = i3 + i4 + i5 + i6 ---- (1) Iin + i5 = i7 ---- (2)

switching speed of these logic gates. Further, the effect of 3

3 d 2

o b

overdrive current on these resistive logic gates has been studied.

i 3 *I *0

2

sin b

C j

2 2

dt 2

--- (3)

1. DEPARTMWENT OF PHYSICS, GMR INSTITUTE OF 3

3 d 2

TECHNOLOGY, RAJAM-532127,A.P., INDIA Email :

i *I*

sin *C*

o a

srinkura@gmail.com srinivas.k@gmrit.org

2. DEPARTMENT OF ELECTRONICS AND ELECTRICAL

4 2 0

a 2 j 2

dt 2

---- (4)

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International Journal of Scientific & Engineering Research Volume 2, Issue 10, Oct-2011 2

ISSN 2229-5518

i 5 *I *0

sin( a c )

d 2

(b) Dynamic case:

Egn.(1) can be written as

C o (

)

*Ig * *I *0 sin ( a c )

j 2

dt 2 a

c

- (5)

3

*I *0

(sin a sin b )

I6 = Vb/RL ----(6)

I7 = Vc/R1 ----(7)

2

Cj o d

( a c )

2 *dt *2

3

d 2

d 2

*C * o ( a b )

2 j

1 o

rL 2

2

db

dt

dt 2

dt 2

--- (8)

o *d**c*

2 *dt*

*r *( *I *in *I *0

d 2

sin ( a c )

--- (9)

o

Fig. 1 Circuit configuration of the resistive logic RCJL

gate with threshold characteristics.

*C *j 2

Also,

dt 2

( a c )

o ( da

2 *dt*

*d*b )

dt

(*I *0 sinb *C *j

--(10)

o d b

2 o

db

I g 1

) *r*

2 *dt *2

3 2 r L dt 3

From Eqns. (8),(9) and (10) we can obtain the following

expressions:

d 2 4

a

Fig. 2 Circuit configuration of the resistive logic RCJL

gate with current indication at each stage of the logic gate

dt 2

I g

3o C j

3

For Static case

( *I *in

2 2

I 0 sin a

------ (II)

At t = 0, Va = Vb = Vc = 0 =>

o

d c

3o

d (a b) )

d a

*d* b *d* x 0

2 *r dt*

4 r 1 dt

dt dt dt

2 2

b

( *I *g o

d (

)

Substituting the above conditions in Eqns. (1) and (2), we

dt 2

o C j

3 2 r1 dt a

b

-- III)

get

I g

I 0

3 (sin

2 a

sinb

) *I *in

I 0

-----(I)

2

*I *0 sin b

3

o

2 *r*L

db ]

dt

Egn.(I) describes the static behaviour of the RCJL gate. A static curve between Ig/10 and Iin/I0 will give the operating margin and gain margins of the RCJL gate.

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International Journal of Scientific & Engineering Research Volume 2, Issue 10, Oct-2011 3

ISSN 2229-5518

d c

2 ( 5 *I*

dt 2

o C j

in

3 3

Fig.3 Simulated switching dynamics of the RCJL gate. Circuit parameters used in the simulation are from

*I *0 sin a

*I *0 sin ( a x )

Nb/A10x/Nb Josephson technology and are given as Io =

0.087 mA, Cj = 0.37 pF, R1 = R2 = R3 = 0.8 , rL = 10 . The

5o

6 *r*

dc

dt

o

2 *r *1

d (

dt a

c

) ) ---- (IV)

switching waveforms of currnet flowing in the input resistor R and the output current respectively.

In Fig.4 we have shown the phase variations with time

Computer-simulated pulse response of the RCJL gate can

be obtained by solving the Eqns. (II),(III) and (IV) for an

input current Iin applied as a step function at t=0 with amplitude 1.5 Ith. To solve these equations the initial

at different stages of the RCJL gate using computer simulation. The biasing and overdrive current conditions are as follows: Ig = 1.510 and Iin 1.510.

Using our concept[6] of turn-on delay, the

conditions for

a ( ao ) and

b ( bo ) are to be known

turn-on delay at each stage of the RCJL gate has-- been

which can be deduced as follows: At t = 0, from Eqns. (1) and (2).

I 3 I

g 2 0

(sin a sin b )

Since the resistances R2 and R3 are equal,

Ig

sin a 0

sin b 0

3*I *0

or a 0

b 0

sin

1 ( *Ig *)

2*I *0

indicated. This will give an exact physical understanding of

Also, at t = 0 ; I in = 0 ==> i5 = 0

switching dynamics of the RCJL logic gate.

==>

sin ( a 0

c 0 ) 0

a 0

ac

Therefore,

a 0

b 0

c0

I

sin 1 ( g )

3 *I *o

The current variations with time for a RCJL gate at each stage have been plotted in Fig.3 using computer simulation.

The solid curve shows the current variation with time at point 'A' (as shown in Fig.2) and the dotted curve shows the output current variation with time.

Fig. 4 Simulated phase evolution vs time for a RCJL

gate. a b and , are the phase variations at points ca’,

‘b’ and ‘c’ respectively. Circuit parameters used in the simulation are I0 = 0.087 mA, Cj = 0.37 pF, R1 = R2 = R3

= 0.8 and rL = 10 .

Further, we have plotted (in Fig.5a and Fig.5b) the

effect of overdrive current on turn-on delay for different biasing conditions Ig = 0.75I0, 1.510 and

2.2510. In Fig.5a and Fig5b the curve (a) indicates the TD vatiation at 4A1 (as shown in Fig.6.2c). Curve (b) shows the TD variation with overdrive at point B1. And curve (c) shows the TD variation at point CI with the overdrive. It can be observed from Fig.5 the turn-on

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International Journal of Scientific & Engineering Research Volume 2, Issue 10, Oct-2011 4

ISSN 2229-5518

delay decreases as the overdrive increases. Also, the turn-on delay decreases with the increase of biasing current and overdrive currents. So, by choosing proper biasing and overdrive current we can minimize the turn- on delay of the RCJL gate.

Finally in Fig.6 we have compared the effect of turn-on delay vs overdrive for JAWS[7], DCI [8] and RCJL gates under the same biasing condition, Ig = 1.510. It is observed for the low fan-out (here fan-out is one) the DCI logic gate seems to be a better choice for the logic circuit application because of its low turn-on delay and high-speed

Fig. 5a Turn on delay of the RCJL gate vs input current. TDa’ TDb and TDc represent the turnon delay variations with time at point ‘a’, ‘b’ and ‘c’ respectively (as shown in Fig. 2).

Fig. 5b

Turn on delay of the RCJL gate vs input current. TDa’ TDb and TDc represent the turnon delay variations with time at point ‘a’, ‘b’ and ‘c’ respectively (as shown in Fig. 2).

Fig. 6.14 Turn on delay vs input current of JAWS, DCI and RCJL gate under same biasing condition, Ig =

1.5I0.

A thorough investigation of RCJL logic gate has been made

. The dynamic response of this logic gate is obtained by

computer-simulation. The concept of our turn-on delay has

been introduced which has helped us in critically

ascertaining the switching speed of the logic gates. The

effect of turn-on delay on overdrive current has been

studied. It is observed that for low fan-outs, the DCI logic

gate and for high fan-out RCJL gate seems to be a better

choice for logic circuit application. It is expected that the

concept of turn-on delay will be able to remove confusions

which are lying in the earlier investigations.

[1] T. R. Gheewala, " Josephson logic devices and circuits," IEEE Trans. Electron Devices vol.ED-27, no.10, October 1980, pp.1857-1869.

[2] T. A. Fulton, S. S. Pei and L. N. Dunkleberger, " A simple high performance current switched Josephson logic," Appl. Phys. Lett. . vol.34, no.10, May 1979, pp. 709-711.

[3] T. R. Gheewala and A. Mukherjee, " Josephson

direct coupled logic (DCL)," IEDM Tech. Dig.,

(Washington DC, December 3-5, 1979), pp. 482-484.

[4] J. Sone, T. Yoshida and H. Abe, " Resistor coupled

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International Journal of Scientific & Engineering Research Volume 2, Issue 10, Oct-2011 5

ISSN 2229-5518

Josephson logic," Appl. Phys. Lett. vol.40, 1982, p.741.

[5] J. Sone, " Turn-on delay analysis of current- injection Josephson circuits," J. Appl. Phys. vol.57, no.ll, June 1985, pp. 5028-5034.

[6] K. Srinivas, J. C. Biswas , " Turn-on delay of a

Josephson junction," J of Low

[7] Tempererature Physics” , vol.74, Nos. 5/6 1989 ,

pp.407-415.

[8] K. Srinivas, J. C. Biswas, “ Dynamic response of

Josephson resistive logic ( JAWS) gate “ , ICECS-11,

INDONESIA (SUBMITTED)

[9] K. Srinivas, J. C. Biswas, “ Dynamic response of Josephson resistive logic ( DCI) gate “ , ICASET-11, SINGAPORE (SUBMITTED)

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