International Journal of Scientific & Engineering Research, Volume 4, Issue 7, July-2013 1864
ISSN 2229-5518
Analysis of Modified Energy Recovery Flip Flops
With Clock Gating
Amit Kumar, Vrinda Gupta
Abstract— Power dissipation has become a important factor while designing the circuits these days. Flip flops are the basic elements in various circuits such as frequency divider circuits, storing devices. So energy recovery flip flops are used nowadays to reduce power dissipation. Certain energy recovery flip flops with clock gating have already been proposed. In this paper certain modifications have been done in these circuits. The circuits have been implemented on design architect. These circuits have been implemented in 180 nanometer technology. The power dissipation has been compared at various clock frequency. The results show considerable reduction in power.
Index Terms— energy recovery flip flops, clock frequency,clock gating, low power, conditional capturing, charge sharing, evaluation path
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Locking is an important aspect and a center piece of digital system design. Not only does it have the high- est positive impact on performance and power, but
also the highest negative impact on the reliability of an improperly designed system. This is becoming more im- portant, as the clock frequency keeps increasing dramati- cally as it has been in the last decade. Thus, Clocking is one of the single most important decisions facing the designer of a digital system. Power dissipation related to the clock generation and distribution is identified as the dominating contributor of the total active power dissipation for multi- GHz systems. As the complexity and size of synchronous systems continues to increase, clock power will also in- crease. This makes novel power reduction techniques ab- solutely crucial in future VLSI design.
Clock gating is a popular technique used in many synchro- nous circuits for reducing dynamic power dissipation.
Clock gating saves power by adding more logic to a circuit
to prune the clock tree. Pruning the clock disables portions of the circuitry so that the flip-flops in them do not have to switch states. Switching states consumes power. When not being switched, the switching power consumption goes to zero, and only leakage currents are incurred. The notion of clock and clocking is essential for the concept of synchro-
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nous design of digital systems. The synchronous system assumes the presence of the storage elements and combi- national logic. The flip flops find their application in fre- quency divider circuit [6]. The paper describes three ener- gy recovery flip flops with clock gating. These flip flops are Single-ended Conditional Capturing Energy Recovery (SCCER) flip-flop, Differential Conditional-Capturing Energy Recovery (DCCER) flip-flop and Static Differential Energy Recovery (SDER) flip-flop.
The topic has been introduced in section 1. Section 2 ex- plains various energy recovery flip flops. These circuits have been simulated in the Design Architect and the re- sults are shown in section 3. The topic has been concluded in section 4.
The best approach for energy recovery clocked flip-flops is to locally generate square wave clocks form a sinusoidal clock. This technique has the advantage that existing square-wave flip-flops could be used with the energy re- covery clock. However, extra energy is required in order to generate and possibly buffer the local square waves. Moreover, energy is not recovered from gate capacitances associated with clock inputs of flip-flops. Recovering ener- gy from internal nodes of flip-flops in a quasi-adiabatic
fashion [1] would also be desirable. However, storage el-
• Mrs Vrinda Gupta is currently Assistant Professor in electronics and com- munication department in NIT Kurukshetra, India,. E-mail: vrind-
a @ mail com
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International Journal of Scientific & Engineering Research, Volume 4, Issue 7, July-2013 1865
ISSN 2229-5518
ements of flip-flops cannot be energy recovering because we assume that they drive standard (non-adiabatic) logic. Due to slow rising/falling transitions of energy recovery signals, applying energy recovery techniques to internal nodes driving the storage elements can result in consider- able short-circuit power within the storage element. Tak- ing these factors into consideration, we developed flip- flops that enable energy recovery from their clock input capacitance, while internal nodes and storage elements are powered by regular (constant) supply.
Figure 1 shows a Single-ended Conditional Capturing Ener- gy Recovery (SCCER) flip-flop. SCCER is a single-ended ver- sion of the DCCER flip-flop. The NMOS transistor MN3, is controlled by the output QB and provides conditional cap- turing. No conditional capturing is required in the right hand side evaluation path and moreover the path is static. Placing MN3 above MN4 in the stack reduces the charge sharing. That is because when the charge sharing occurs, the capacitance associated with MN3 is already charged and therefore does not contribute to the charge sharing [2]. The energy recovery flip flop can also be dual edge triggered [5]. The flip flop dissipates the same amount of power during sleep mode and the active mode. A major portion of the power is dissipated by the clock network. We can save power by disabling the clock network during the sleep mode as significant amount of power is con-
sumed by the clock network. We can disable the clock network by implementing the clock gating due to this for some time, the circuit gets disable. This Figure 1 shows SCCER with clock gating. Clock gating was implemented by replacing the inverter with the NOR gate. The NOR gate has two inputs: the clock signal and the enable signal. In the active mode, the enable signal is low so the NOR gate behaves just like an inverter and the flip-flop operates just
like the original flip-flop. In the idle state, the enable signal is set to high which disables the internal clock by setting the output of the NOR gate to be zero. This turns off the pull down path (MN2) and prevents any evaluation of the data. Hence, not only the internal clock is stopped (clock power saving) but also all the internal switching is pre- vented (power saving on data circuits). The skewed invert- er was replaced by a NOR gate. It should be mentioned
that the skew direction for the
Figure 1: SCCER Flip Flop
NOR gate should remain as that in the original inverter
gate (skewed for high to low transition; pull-down network stronger than pull-up).
Figure 2 shows the Differential Conditional-Capturing En- ergy Recovery (DCCER) flip-flop. Similar to a dynamic flip- flop, the DCCER flip-flop operates in a pre-charge and evaluates fashion. However, instead of using the clock for
pre-charging, small pull-up PMOS transistors (MP1 and
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International Journal of Scientific & Engineering Research, Volume 4, Issue 7, July-2013 1866
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MP2) are used for charging the pre-charge nodes (SET and
RESET). The DCCER flip-flop uses a NAND-based Set/Reset
latch for the storage mechanism. The conditional captur- ing is implemented by using feedback from the output (Q and QB) to the control transistors MN3 and MN4 in the evaluation paths. Therefore, if the state of the input data (D and DB) is same as that of the output (Q and QB), both left and right evaluation paths are turned off preventing SET and RESET from being discharged. This results in pow- er saving at low data switching activities when input data remains idle for more than one clock cycle [2].
Figure 2: DCCER Flip Flop
Figure 3 shows the Static Differential Energy Recovery (SDER) flip-flop. This flip-flop is a static pulsed flip-flop sim- ilar to the Dual-rail Static Edge-Triggered Latch (DSETL) [3].
Figure 3: SDER Flip Flop
A cascade of three inverters instead of one can give a slightly sharper falling edge for the inverted clock (CLKB). However, due to the slow rising nature of the energy re-
covery clock, enough delay can be generated by a single inverter. In this flip-flop, when the state of the input data is the same as its state in the previous conduction phase, there are no internal transitions. Therefore, power con- sumption is minimized for low data switching activities.
The second approach for minimizing flip-flop power at low
data switching activities is to use conditional capturing [4] to eliminate redundant internal transitions [2]. Power re- sults show significant savings when the clock gating is ap-
plied to the flip-flop during the idle state.
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International Journal of Scientific & Engineering Research, Volume 4, Issue 7, July-2013 1867
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In the SCCER flip flop discussed above, the gate terminal of the PMOS (MP1) is connected to ground terminal. If the terminl is connected to the gate of (MP2), power reduc- tion occurs. Similarly in the DCCER flop, the gate terminals of MP1 and MP2 are connected to their drain terminals. The modified circuit helps to reduce charge sharing as the clock transistor (MN1), which is the largest transistor in
the evaluation path, is placed at the bottom of the stack.
Therefore, the diffusion capacitance of the source terminal of MN1 is grounded and does not contribute to the charge sharing. Although MP1 and MP2 are statically ON, they do not result in static power dissipation because as soon as
the data sampling finishes and Q obtains the values of D,
the pull down paths get turned off and the SET and RESET nodes are pulled back high without any static power dissi- pation. In SDER flip flops the two transistors are removed, thereby reducing area overhead. In this flip-flop, when the state of the input data is the same as its state in the previ- ous conduction phase, there are no internal transitions.
Therefore, power consumption is minimized for low data switching activities.
All the circuits have been implemented in Design Architect and on 180 nanometer. Here 180 nanometer specifies the channel length. Figure 4 shows the reported SDER energy recovery flip flop in [2] and its modified form is shown in
figure 5.
Figure 4: Reported SCCER Flip Flop
Figure 5: Modified SCCER Flip Flop
It can be seen from the figure that gate terminal of up- per most PMOS transistor. Here the blocks used are in- verter and nor gates. Figure 6 and figure 7 shows the schematic of reported DCCER flip flop and modified flip flop.
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International Journal of Scientific & Engineering Research, Volume 4, Issue 7, July-2013 1868
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Figure 6: Reported DCCER Flip Flop 
The modified SDER flip flop makes a substantial reduction
in area requirement and it can be shown from figure be- low. Figure 8 shows the conventional SDER flip flop with the clock gating and figure 9 depicts the modified version
of SDER flip flop.
Figure 7: Modified DCCER Flip Flop
Figure 8: Conventional SDER Flip Flop
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International Journal of Scientific & Engineering Research, Volume 4, Issue 7, July-2013 1869
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Figure 9: Modified SDER Flip Flop
These circuits have been implemented at various clock frequencies. The variation of power for SCCER Flip Flop along with the frequency is given as below in the table 1
Table 1: Power consumption in SCCER flip flop
Table 2 shows the power consumption of modified DCCER flip flop and conventional flip flop at various clock fre- quencies. The frequency is in Mega Hertz and the power is in micro watt.
Frequency (MHz) | Conventional (uW) | Modified (uW) |
100 | 30.76 | 23.45 |
150 | 40.23 | 29.50 |
200 | 59.36 | 43.56 |
250 | 67.35 | 45.29 |
Table 2: Power consumption in DCCER Flip Flop
The same results have been obtained for SDER Flip Flop and these results too show considerable reduction in power dissipation when clock gated circuit is taken into
account. These results are shown in table 3.
Frequency (MHz) | Conventional (uW) | Modified (uW) |
100 | 45.67 | 34.98 |
150 | 49.21 | 45.10 |
200 | 61.70 | 47.37 |
250 | 65.93 | 48.25 |
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• Mrs. Vrinda Gupta is currently Assistant Professor in electronics and com- munication department in NIT Kurukshetra, India,E-mail: vrind-
@ mail com
IJSER © 2013 http://www.ijser.org
International Journal of Scientific & Engineering Research, Volume 4, Issue 7, July-2013 1870
ISSN 2229-5518
200 | 56.52 | 45.48 |
250 | 61.97 | 52.17 |
Table 3: Power consumption in SDER Flip Flop
`Clock gating is an important technique for power reduction. This technique has been implemented in various energy re- covery flip flops.The results show considerable reduction in power when employed with the concept of clock gating. . These circuits also find their use in frequency divider circuits which are used in microproceser, to reduce the power consid- erably.
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