International Journal of Scientific & Engineering Research Volume 2, Issue 6, June-2011 1
ISSN 2229-5518
A Novel Scheme to Eliminate Common Mode
Voltage in Multilevel Inverters
Nasim Rashidi-rad, Abdolreza Rahmati, Adib Abrishamifar
—————————— • ——————————
1 INTRODUCTION
ultilevel inverters are receiving increased attention recently, especially for use in high power applications. This increased attention is probably due to the fact that the output waveforms are much improved
over those of the two level inverters.
The staircase waveform of multilevel inverters which is composed of several levels of dc voltages, will lead to
The following sections of the paper present the algorithm of this method and simulation results in a five level inverter.
In an N-level inverter, each phase voltage can produce an N-level staircase waveform. Therefore line voltages of this inverter which is the subtraction of two phase
voltages will have 2N-1 levels.
higher output voltage and lower stress on power
switches. Furthermore by increasing the levels of output
Vab
= Va
- Vb
voltage, the waveform contains lower harmonic contents
Vbc = Vb - Vc
(1)
that will lead to reduce the requirements of output filter.
Vca
= Vc
- Va
Therefore multilevel inverters have been selected as a
preferred power inverter topology for high voltage and high power applications [1-4].
All multilevel PWM inverters such as conventional two
The average of line voltages with 120 degree phase difference will be zero at each moment.
level inverters generate common-mode voltage within
Vab +Vbc +Vca = (Va -Vb ) + (Vb -Vc ) + (Vc -Va ) = 0
(2)
the motor windings. This voltage may result in motor and drive application problems [5].
This paper presents a method in multilevel inverters, which is based on space vector diagram in an imaginary inverter. This scheme completely eliminates common- mode voltages and will be applicable for any general
Therefore if line voltages of one imaginary inverter will be used as phase voltages of another inverter, the momentary average of the phase voltage of the second inverter will be always zero. To achieve this, the following equations are necessary to be valid in the
system:
circuit configuration.
if V
Line ( N I Level )
= V Phase ( N Level ) �
————————————————
\(2 N I - 1 = N
i
(3)
I N. Rashidi-rad, Iran University of Science and Technology, Iran, E-mail: Nasim83.iust@gmail.com
\ 3 ( N I - 1)VC ( N Level ) = ( N - 1)VC ( N Level )
I A. Rahmati, Iran University of Science and Technology, Iran, E-mail: � V
( N - 1)V
= C ( N Level )
I A. Abrishamifar, Iran University of Science and Technology, Iran, E-mail:
C ( N I Level )
3 ( N I
- 1)
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International Journal of Scientific & Engineering Research Volume 2, Issue 6, June-2011 2
ISSN 2229-5518
Therefore it can be concluded that if line voltages of an (N+1)/2 level inverter will be used as phase voltages of an N level inverter, then the common mode voltage of the N level inverter will become zero.
In other words, each voltage vector in the space vector diagram of the (N+1)/2 level inverter will be corresponded to the voltage vectors with zero common mode voltage in an N level inverter. Therefore the number of all voltage vectors in an (N+1)/2 level inverter is equal to the number of voltage vectors with zero common mode voltage in an N level inverter.
It should be noted that since (N+1)/2 is an positive integer
number, N cannot become an even number; this means that for an even N, an N level inverter cannot have zero common mode voltage.
In the following paragraphs, the relations between
number of vectors and switching states for an N and
(N+1)/2 level inverters has been presented.
Based on table 1, the number of switching states in a three phase N level inverter will be N 3 . Among these states, the number of voltage vectors will be calculated
based on following relations.
N V ( N =1)= 1,
NV ( N ) = NV ( N -1) + 6( N - 1) �
(4)
NV ( N = 2) = 7 , NV ( N = 3) = 19 , ...
Therefore the number of voltage vectors with zero common mode voltage in an N level inverter can be calculated as:
Figure 1. Circuit configuration of (a) one phase leg of a five level modular inverter, (b) a half-bridge cell
According to the proposed scheme, phase voltages of the
NVectors With Vcom =0 ( N ) = NV (( N +1) / 2 )
(5)
5level inverter will be composed by line to line voltages
3 RESULTS
This scheme has been explained for a 5level modular inverter, which has been utilized to drive a 400 volt
motor. Therefore the space vector diagram which has
of the 3level inverter. So in these equations Va ,Vb
Vc are phase voltages and:
Va (5level ) = Va (3level ) - Vb (3level )
Vb (5level ) = Vb ( 3level ) - Vc (3level )
and
(7)
been used, belongs to the 3level inverter and
Vc (5level )
= Vc (3level )
- Va (3level )
V
TOTAL
= 600v .
The definition of the common mode voltage is:
if V Line ( 3 level ) = VPhase ( 5 level ) :
4V 2V
Vcom( 5level)
= Va (5level ) + Vb( 5level) + Vc (5level ) �
3
(8)
2VC ( 3 level ) =
C ( 5 level )
3
� VC ( 3 level ) =
C ( 5 level )
3
(6)
Therefore:
V
TOTAL
= ( N - 1)VC ( N Level ) ,
N = 5 �
Vcom(5level ) = 0
(9)
VC ( 5 level ) = 150 v
� VC ( 3 level ) = 173 .2v
Considering the elimination of common mode voltage in the 5level inverter, it can be concluded that it won’t be
TABLE I. RELATIONS BETWEEN NUMBER OF VECTORS
AND SWITCHING STATES
dependent to the modulation method which is utilizing in the imaginary 3level inverter.
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International Journal of Scientific & Engineering Research Volume 2, Issue 6, June-2011 3
ISSN 2229-5518
Another conclusion is that redundant switching states as shown in figure 2, will have similar results. For instance if the selected modulation method in 3level inverter will be based on delivering nearest vector to the reference vector, election each of switching states of (2,1,1) or (1,0,0) will lead to zero common mode voltage and equal output voltages in the 5-level inverter. Furthermore among three switching states for zero vector, the vector of (1, 1, 1) has
been selected.
150
100
50
0
0.4 0.6 0.8 1 1.2
Modulation Index
In this stage, selecting a suitable modulation method in the imaginary 3level inverter, that has a rather low harmonic distortion and a good linearity relationship is highly important. But it should be noted that reducing or eliminating of common mode voltage in the selection of the modulation method won’t be considered.
Therefore one of the major advantages of the proposed
method is its independency in selection of modulation method of the (N+1)/2 level inverter.
Since elimination of common mode voltage in SPWM
methods usually is more difficult than SVM methods, the proposed scheme can be utilized to eliminate the common mode voltage in SPWM methods. Figure 4 has shown phase and line and also common mode voltage in the 5level inverter utilizing an SPWM method.
It should be noted that the selective carrier based modulation is PD (Phase Disposition) method, which has
the same phases of two adjacent carriers [6].
Figure 3. Total harmonic distortion in the 5level inverter, for both diagrams of figure 2
(a)
2
1.5
1
0.5
020
010
110
110
0 011
-0.5
-1
011
001
111
101
100 200
(b)
-1.5
-2
002 101
-2 -1 .5 -1 -0.5 0 0.5 1 1.5 2
(a)
2
1.5
1
0.5
020
121
221
110
(C)
Figure 4. (a) phase voltages, (b) line voltage, and (c) common mode voltage in the 5level inverter by an SPWM method (PD)
0
-0.5
-1
-1.5
011
122
111
112 212
211
200
This paper has proposed a novel scheme to generate
002 101
-2
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
(b)
Figure 2. Considering of redundant switching states in space vector diagrams of the 3level inverter
pulse width modulation signals for multilevel inverters. This scheme which can be used in inverters with an odd number of levels will reduce the common mode voltage to zero.
The main idea of the scheme is based on zero momentary
average of line voltages in each inverter. Therefore by
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International Journal of Scientific & Engineering Research Volume 2, Issue 6, June-2011 4
ISSN 2229-5518
utilizing the line voltages of an imaginary inverter as phase voltages of the real inverter, the common mode voltage of the real inverter will be zero.
Furthermore it can be concluded that the number of all
voltage vectors in the imaginary inverter will be equal to the number of voltage vectors with zero common mode voltage in the real inverter.
Independency of this scheme in selection of SPWM or SVM methods for the imaginary inverter is one of its major advantages.
The proposed method has been shown for an inverter
with 5level voltage. It should be noted that this method can be easily extended to higher levels.
[1] Nikola Celanovic, DushanBoroyevich, “A Fast Space-Vector
Modulation Algorithm for Multilevel Three-Phase Converters”,
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL.37, NO.2, MARCH/APRIL 2001
[2] Aziz, J.A, Salam, Z. “A PWM Strategy for the Modular
Structured Multilevel Inverter Suitable for Digital Implementation”,
2002 IEEE.
[3] Sanmin Wei and Bin Wu, Fahai Li and Congwei Liu “A General
Space Vector PWM Control Algorithm for Multilevel Inverters”,
2003 IEEE.
[4] “Investigation and Comparison of Multi-Level Converters for
Medium Voltage Applications”, Seyed Saeed Fazel, Berlin 2007
[5] Haoran Zhang, Annette von Jouanne, Shaoan Dai, Alan K.Wallace, Fei Wang, “Multilevel Inverter Modulation Schemes to Eliminate Common-Mode Voltages”, IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 36, NO. 6, NOVEMBER / DECEMBER 2000.
[6] Zhou Jinghua, Li Zhengxi, “Research on Multi-carrier PWM Modulation Strategies of Three-level Inverter”
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