Author : Rashmi K. Lomte (Mrs.Rashmi R. Kulkarni), Prof.Bhaskar P.C

International Journal of Scientific & Engineering Research, Volume 2, Issue 5, May-2011

ISSN 2229-5518

Download Full Paper : PDF**Abstract— **Deconvolution is a computationally intensive digital signal processing (DSP) function widely used in applications such as imaging, wireless communication, and seismology. In this paper deconvolution of two finite length sequences (NXM), is implemented using direct method to reduce deconvolution processing time. Vedic multiplier is used to achieve high speed. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. For division operation non-restoring algorithm is modified and used. The efficiency of the proposed convolution circuit is tested by embedding it on Spartan 3E FPGA. Simulation shows that ,the circuit has a delay of 79.595 ns from input to output using 90nm process library. It also provides the necessary modularity, expandability, and regularity to form different deconvolutions for any number of bits.

**Index Terms—** Deconvolution, Non-Restoring algorithm, Urdhva Tiryagbhyam

**1 INTRODUCTION ** THE concept of deconvolution is widely used in the techniques of signal processing and image processing. The concept of deconvolution has applications in reflec-tion seismology, in reversing the optical distortion, to sharpen images etc. Faster additions, multiplications and divisions are of extreme importance in DSP for deconvolution. Speeding up deconvolution using a Hardware Description Language for design entry not only increases (improves) the level of abstraction, but also opens new possibilities for using programmable devices.

In this paper, a novel method for computing the li-near deconvolution of two finite length sequences is used. Method is explained in detail in [1]. This method is similar to computing long-hand division and polynomial division.

As a need of project, all required possible adders are studied. All these adders are synthesized using Xilinx9.2i. There delays and areas are compared. Adders which have highest speed and comparatively less area occupied, are selected for implementing deconvolution. Since 4×4 bit multiplier is need of this project, different 4×4 bit multipliers are studied and Urdhava Triyakbhyam algorithm which gives lowest delay among remaining all multipliers is used here. For division, different division algorithms are studied, by comparing drawbacks and advantages of each algorithm, Non restoring algorithm is modified ac-cording to need and then used.

This paper can be considered as extension of [2]. where discrete linear convolution of two finite length sequences(4 ×4) is implemented. That convolved output of [2]. is input to this proposed design, impulse re-sponse of system is known is another input, this paper proposes design that carry out high speed deconvolution and extracts input samples.

Paper is organized as follows: section 2 gives brief in-troduction of novel method for deconvolution. Section 3 describes division algorithm. Section 4 discusses the Vedic mathematics and Urdhva Tiryagbhyam algo-rithm for multiplication. Section 5 presents selection of speedy adder. In section 6 design verification is given. Finally, the conclusion is obtained.

**2 NOVEL METHOD FOR CALCULATING DECONVOLUTION** In general, the object of deconvolution is to find the solution of a convolution equation of the form:

Usually, h is some recorded signal, and ƒ is some signal that wish to recover, but has been convolved with some other signal g before get recorded. The function g might represent the transfer function of an instrument or a driving force that was applied to a physical system.If one know g or at least form of g,then one can perform deterministic deconvolution.

This recursion can be carried out in a manner similar to

long division. Lets take example ,let h[n] = [16 36 56 17 28 12 ] and g[n] = [ 4 4 3 2 ] , solving for f(n) given g(n) and h(n). The sequences are set up in a fashion similar to long division, as shown below, but where no carries are performed out of a column.

By observing figure 1. one can easily predict, for im-plementing speedy deconvolution by above method, divisor , multiplier and adder(to achieve subtraction in form of addition) used in design must be speedy.

High speed division can be carried out by selecting proper division algorithm.Vedic multiplier is used to get speedy multiplication.

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