Author Topic: Volume 4, Issue 4, April 2013 , By Dr. Chhavi Saxena  (Read 2972 times)

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Volume 4, Issue 4, April 2013 , By Dr. Chhavi Saxena
« on: April 12, 2014, 01:53:52 pm »
Itís no secret that power is emerging as the most critical issues in system-on-chip (SoC) design today. Power management is becoming an increasingly urgent problem for almost every category of design, as power density-measured in watts per square millimeter-rises at an alarming rate.
Moving a design from an old technology to a newer one, with smaller design rules, has always been, up to now, an interesting way to lower the power consumption. Indeed, the overall parasitic capacitances are decreased, the available active current per device is higher, and, consequently, the same performance can be achieved with a lower supply voltage. Moving to a new technology generation, however, induces a scale down of the power supply voltage (VDD), the threshold voltage (VT), and the gate oxide thickness (TOX). Beginning with the 0.18μm technologies, it appeared that building a transistor with a good active current (ION) and a low leakage current (IOFF) was becoming more difficult. Since the advent of CMOS technology, an increased number of transistors per die and greater performance have been the primary driving factors for the semiconductor industry and process technology. The ability to integrate more transistors per die allowed chip manufacturers to put more components of a system into a single package and thus reduce not only just the sizes of the electronic devices we use today but also the cost and delay. The intense competition in the semiconductor industry has forced chip manufacturers pursue these great goals.
However, the increase in the number of devices due to the increase in device density has more than compensated for the decrease in the parasitic capacitance of a single device. In addition to shortened battery life for portable electronics, higher power consumption results in aggravated on-chip temperatures, which can result
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in a reduced operating life for the IC. For portable electronics, longer battery life is the most important design constraint.

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