Author Topic: SAT Implementation in Direct Torque Control For Dynamic Response in Multi Level  (Read 3620 times)

0 Members and 2 Guests are viewing this topic.

IJSER Content Writer

  • Sr. Member
  • ****
  • Posts: 327
  • Karma: +0/-1
    • View Profile
Author : Rohithbalaji Jonnala
International Journal of Scientific & Engineering Research Volume 3, Issue 1, January-2012
ISSN 2229-5518
Download Full Paper : PDF

Abstract— This paper presents the implementation of Direct Torque Control (DTC) with Sector Advancement Technique (SAT) algorithm for the control of a Hybrid Cascaded H-Bridge Multilevel Inverter Induction motor Drive. It is useful to keep the motor torque and stator flux and the inverter’s neutral point potential within given hysteresis bounds while reducing the average switching frequency of the inverter and overall computational time period comparison with the standard direct torque control (CDTC). This method also improving overall efficiency with Torque and Flux ripple reduction. In addition, the multilevel inverter can generate a high and fixed switching frequency output voltage with fewer switching losses, since only the small power cells of the inverter operate at a high switching rate. Therefore, a high performance and also efficient torque and flux controllers are obtained, enabling a DTC solution for multilevel-inverter-powered motor drives.

Index Terms— Direct Torque Control (DTC), Multi Level Inverter, Induction Motor Drives, Sector Advancement Technique (SAT). 

Since its introduction, direct torque control (DTC) has become a powerful control scheme for the control of induction motor (IM) drives. The standard DTC scheme uses hysteresis comparators for the control of both stator flux magnitude and electromagnetic torque. This control structure ideally keeps both controlled parameters within the hysteresis bands and results in a non constant switching frequency. One of the methods that have been used by one major manufacturer in multilevel inverters is direct torque control (DTC), which is recognized today as a high-performance control strategy for ac drives. Several authors have addressed the problem of improving the behaviour of DTC ac motors, particularly by reducing the torque ripple. However, when the DTC scheme is used in a discrete implementation, both torque and flux exceed the bands imposed by the hysteresis comparators, due to the fixed sampling frequency. It is possible for the discrete scheme to operate as an analogy one if the hysteresis bounds are chosen to be sufficiently large. On the contrary, when the width of the bands is comparable to the maximum torque and flux variations during one sampling period, the excursions will be relatively large, partly due to the time delay that is caused by the data processing. Therefore, the sampling period is an important factor determining the control performance and switching frequency.

   To improve the performance of control operation, different approaches have been proposed: improving the lookup table; varying the hysteresis bandwidth of the torque controller; and using flux, torque, and speed observers. Although these approaches are well suitable for the classical two-level inverter, their extension to a greater number of levels is not easy. Throughout this paper, a theoretical background is used to design a simple and practical strategy that is compatible with hybrid cascaded H-bridge multilevel inverter. It allows not only controlling the electromagnetic state of the motor with improved performance (minimization of the torque ripple) but also reducing flux and current distortion caused by flux position sector change.
To improve the flux waveform, ripple free torque, dynamics and efficiency of the drive and to enhance the quality of stator currents in the motor. Sector Advancing Technique (SAT) is employed for reducing the response time of the drive to given torque command.

   The hybrid cascaded H-bridge inverter is composed of three legs, in each one is a series connection of two H-bridge inverters fed by independent dc sources that are not equal (V1 < 2).Indeed, it may be obtained from batteries, fuel cells. The use of asymmetric input voltages can reduce, or when properly chosen, eliminate redundant output levels, maximizing the number of different levels generated by the inverter. Therefore, this topology can achieve the same output voltage quality with fewer numbers of semiconductors.

The use of asymmetric input voltages (inverter fed by a set of dc-voltage sources where at least one of them is different from the other one) can reduce, or when properly chosen, eliminate redundant output levels, maximizing the number of different levels generated by the inverter.

  Figure 2: Voltage Vector formation in Multilevel Inverter

 Therefore, this topology can achieve the same output voltage quality with fewer numbers of semiconductors. The maximum number of redundancies is equal to (3K −2K − 1) and can be obtained when the partial dc voltages are equal to E/ (N − 1). If there is 2K connected cells per multilevel-inverter phase leg, 3K switching configurations are possible and N is number of levels.

Figure 3: Basic H-Bridge Structure
The multilevel-inverter output voltage depends on the partial voltage feeding each partial cell. The possible number of redundant switching states can be reduced if the cells are fed by unequal dc-voltage sources. This also reduces volume and costs and offers inherent low switching losses and high conversion efficiency. When cascading two-level inverters like H-bridges [Fig3], the optimal asymmetry is obtained by using voltage sources proportionally scaled to the two- or three-H-bridge power. Particular cell i can generate three levels (+Vi, 0, −Vi). The total inverter output voltage for a particular phase j is defined by

v_jN=∑_(i=1)^m▒〖v_jN=∑_(i=1)^m▒〖V_i (S_i1-S_i2)〗             j∈{a,b,c}〗  ………(1)

Where νij is the i cell output voltage, m is the number of cells per phase, and (Si1, Si2) is the switching state associated to the i cell. Equation (1) explicitly shows how the output voltage of one cell is defined by one of the four binary combinations of switching state, with “1” and “0” representing the “ON” and “OFF” states of the corresponding switch, respectively. The optimal asymmetry is obtained with dc links scaled in powers of two or three, generating seven or nine different output levels. Nine different output levels can be generated using only two cells (eight switches); while four cells (16 switches) are necessary to achieve the same amount of level with a symmetric-fed inverter.

Read More: Click here...