Author Topic: Dynamic Response Of Jospephson Resistive Logic (RCJL) Gate  (Read 2607 times)

0 Members and 1 Guest are viewing this topic.

IJSER Content Writer

  • Sr. Member
  • ****
  • Posts: 327
  • Karma: +0/-1
    • View Profile
Dynamic Response Of Jospephson Resistive Logic (RCJL) Gate
« on: November 23, 2011, 07:35:40 am »
Quote
Author : K.SRINIVAS and J. C. BISWAS
International Journal of Scientific & Engineering Research Volume 2, Issue 10, October-2011
ISSN 2229-5518
Download Full Paper : PDF

ABSTRACT----In this paper a thorough investigation of resistive logic RCJL gate has been made. The current equations of this gate at each stage have been deduced. The dynamic response of this gate has been obtained by the computer-simulation. Our concept of turn-on delay has been introduced. The effect of overdrive current on turn-on delay for resistive logic gate has been shown. This will provide a better understanding of switching dynamics of the RCJL logic gate. Further, we have shown the effect of overdrive current on this logic gate.
 
1. INTRODUCTION
Two attractive features of SQUID devices for logic applications are isolation and serially connected fan-out. The isolation is provided by the transformer coupling between the SQUID and the input. The isolation is not perfect in the sense that a noise pulse (typically 5 percent) is fed back into the control line when the SQUID switches to the non-zero voltage. The other advantage is the serial fan-out capability by which the control lines of many load devices can be connected in series with a single output line.
The main drawbacks of SQUID devices for logic application are relatively large device area and high sensitivity to stray magnetic fields. In SQUID 80% of the area is occupied by the transformer [1]. Further, the high sensitivity to stray magnetic field requires that the SQUID based logic circuits be well shielded from the stray magnetic fields.
The resistive logic gates such as JAWS (Josephson Auto-Weber System) [2], DCI (Direct Coupled Isolation) [3] and RCJL (Resistor Coupled Josephson Logic) [4] are chosen because the gate logic delay in this case would consist of the turn-on delay, switching delay and propagation delay, but not the crossing delay as in the case of magnetically coupled logic gates. Further, these resistive logic gates do not have a factor of limiting the size very seriously. So, the gate propagation delay can be made sufficiently small. Therefore, the small time constant of the Josephson junction can be directly attained to these gates.
It has been considered by the earlier workers [5] that the turn-on delay of a logic gate is the time taken for the logic gate to obtain 2% of the output current to the load. This consideration seems to be arbitrary.
Due to this fact, in the present paper we have made a thorough investigation of the resistive logic gates. Our concept of turn-on delay [6] has been introduced which will be able to remove the confusion in critically ascertaining the switching speed of these logic gates. Further, the effect of overdrive current on these resistive logic gates has been studied.

2. RCJL (Resistor Coupled Josephson Logic)
The curcuit configuration and the threshold curve for the RCJL gate are shown in Fig.l. The junctions J1, J2 and J3 have critical currents Io, 3/2 Io, and 3/2 Io, and junction capacitances of Cj, 3/2 Cj, and 3/2 Cj, respectively. The resistor R2, R3 and R4 have the same values of the resistance r' and the    resistance of R1 is r. The RCJL gate is biased in the superconducting state by the injection of the input current Iin. The junction J2 plays a role of the current-summing junction in this gate. The operation of the RCJL gate is as follows:
Intially the gate current Ig splits into Igl  and I g2   in the inverse ratio of resistors r2 and r3. When the input current Iin (Ic) is applied at the node C, the Iin goes through the junction J1 and is injected into the junction J2. The junction J2 subsequently switches from the superconducting state to the resistive state. A fraction of the Josephson current having shown in J2, swings over the junction J3 through r2, r3, r4, and causes J3 to switch. Consequently, the gate current Ig is steered towards the junction J1, and J1 switching results. After J1 switching, Ig is steered into the load Rl and I in is teriminated through Rl.   Gate switching with   input-output isolation is completed. In the RCJL gate, total Iin   current contributes to initialization of the switching sequence, while only a fraction of Ig contributes to it. This results in a high input sensitivity.

Read More: Click here...