Author Topic: Fault Modeling of Sequential Circuits at Register Transfer Level  (Read 2564 times)

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Fault Modeling of Sequential Circuits at Register Transfer Level
« on: November 23, 2011, 02:18:46 am »
Author : Suma M.S,K.S.Gurumurthy
International Journal of Scientific & Engineering Research Volume 2, Issue 10, October-2011
ISSN 2229-5518
Download Full Paper : PDF

Abstract— As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tougher. As of now fault models are used to test digital circuits at the gate level or below that level. By using fault models at the lower levels, testing becomes cumbersome and will lead to delays in the design cycle. Thus there is a need to look for a new approach of testing the circuits at higher levels to speed up the design cycle. This paper proposes on Register Transfer Level (RTL) modeling for digital circuits and computing the fault coverage. The result obtained through this work establishes that the fault coverage with the RTL fault model is comparable to the gate level fault coverage.

Index Terms— fault coverage,fault list,fault models,fault simulation,RTL,stuck-at fault,test patterns. 

1   INTRODUCTION                                                                     
VLSI industry is growing as per Moore’s law and integrated circuit designs are accordingly becoming more and more complex. As a result of this, VLSI testing has become expensive in terms of cost. Existing gate level fault simulation techniques exhibit poor performance standards when applied to such designs and are unsuitable for early testability analysis or fault simulations. Also test generation and fault simulation efforts in the post synthesis phase do not contribute to the improvement in the design. Therefore a design methodology for fault simulation at higher levels of abstraction is highly desired.
Many high-level fault models and fault simulation techniques have been proposed. No single fault model is universally acceptable since no fault model has been developed so far that comprehensively covers all classes of circuits. The RTL description is at a higher level of abstraction and may not cover all the gate level faults [2].
The fault model proposed by F.Corno, G.Cumani, M.Sonza Reorda and G.Squillero [2] adopts a particular instantiation of the observability enhanced statement coverage metric in addition to the single stuck-at bit faults on all assignments targets of the executed state-ments. The model implies observability enhanced statement coverage by modeling one of the possible fault classes on executed statements. This is an incomplete modeling of the various faults associated with the RTL description of the circuit.
The fault model by Barry W. Johnson is developed via abstraction of industry standard single-stuck-line (SSL) faults into the behavioral domain. A functional analysis technique was used to evaluate the effects of the SSL faults on gate-level implementation. Since the gate-level netlist changes drastically during logic synthesis, the authors in [3] concluded that modeling all possible gate- 

level faults at the RTL is highly inefficient.
The RTL fault model and simulation approach pro-posed by Mao and Gulati [4] uses the single stuck-at fault for each bit of all variables in the RTL model. The model employs both the RTL description and functional verification patterns. But their approach required one to run fault simulation twice, first in an optimistic mode and then in the pessimistic mode and to use the average of the results to reduce the difference between the RTL and the gate-level fault coverage. The experimental data shows as much as 10 % error be-tween the actual gate-level fault coverage and the RTL fault coverage.
Another fault model proposed by Devadas and Ghosh [5] is the Observability Enhanced Statement Coverage Metric. This model requires that all statements in the RTL description are executed at least once and that their effects are propagated to at least one primary output. As this approach can be fruitfully exploited for the test pattern for fault simulation, more accurate results are needed.
The fault model proposed by Karunaratne et al. [6] does not consider stuck-at faults in the signal bit values and also not account for these faults. Also the process of locating the RTL faults and mapping them to the corresponding Gate-Level faults is to be done. It is therefore desirable to develop the fault model at a higher level of abstraction than the gate level. Fault Simulation and testing at the higher levels of abstraction have a better chance of being integrated well into the overall design process.
Jose M.Fernandes et al.[7] has proposed a new proba-bilistic method for controllability evaluation based on a traitorously selection of registers to form groups. This work needs further optimization by computing the probabilistic impact of the simultaneous correction of different testability problems.
In this work Verilog Hardware Description Language is used for writing the RTL models. The basic assumption is that the components are fault free and only their interconnections are affected. These map to the operators and variables in the RTL descriptions respectively. Gate level primitives can be instantiated in a model using gate instantiation as these are supported for synthesis. These primitive gates describe the hardware. Therefore synthesizing a gate primitive generates logic based on the gate behavior which eventually gets mapped to the target technology [1].Based on this the single stuck-at fault is modeled.The assumption is also that at most one fault occurs at a time in the circuit.
The proposed fault model is an improvement over the model given by Karunaratne et al.[6].Stuck-at faults in the signal bit values was not considered and accounted. Also the process of locating the RTL faults and mapping them to the corresponding Gate-Level faults was not implemented.
The analysis flow for the modeling approach is of two ways as shown in Fig. 1. One way targets on the gate-level fault coverage while the other is on the RTL fault coverage. In the RTL path, the RTL design description is obtained based on the specification. Since the fault model is at the RTL, the fault is induced at the input and at the output. This is done by using a buffer for each bit in all of the variables in the RTL code. These buffers are inserted in the fault free circuit and should not disturb the functionality of the code. As a result, a modified faulty RTL circuit is obtained. To enable fault simulation the process of generating faulty circuits by inducing faults into the fault-free circuit is done. For each of the faults a new circuit is created.
Testbench is developed and the simulation is first run on a good circuit and then on each of the faulty circuits using any simulator. The outputs obtained in each case of the faulty circuits are compared with the output of the good circuit to determine which faults are detected. That is the new faulty circuit and the fault free circuit is simulated and the outputs so obtained are compared. The fault list is tabulated. The ratio of the numbers of RTL faults detected to the total number of RTL faults gives the RTL fault coverage. For each RTL design descriptions gate level implementations are obtained for 65 nanometer target technology using logic synthesis tool and fault cover
age obtained by Tetramax tool. The fault list of both the RTL as well as Gate-Level faults is compared. The ef-fectiveness of our fault model is determined by compar-ing RTL fault coverage with the fault coverage obtained at the gate level.

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