Author Topic: Design and Performance analysis of a 3GPP LTE/LTE-Advance turbo decoder using so  (Read 1978 times)

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Author : Lohith Kumar H G, Manjunatha K N, Suma M S, C K Raju, Prof.Cyril Prasanna Raj P
International Journal of Scientific & Engineering Research Volume 2, Issue 6, June-2011
ISSN 2229-5518
Download Full Paper : PDF

Abstract— This paper presents the design and development of an efficient VLSI architecture for 3GPP advanced Turbo decoder by utilizing the convolutional interleaver. The high-throughput 3GPP Advance Turbo code requires turbo decoder architecture. Interleaver is known to be the main obstacle to the decoder implementation and introduces latency, due to the collisions it introduces in accesses to memory. In this paper, we propose a low-complexity soft Input Soft Output (SISO) turbo decoder for memory architecture to enable the Turbo decoding that achieves minimum latency. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed Turbo decoder has been modeled using Simulink; various test cases are used to estimate the performances. The results are analyzed and achieved 50% reduction in computation time along with reduced BER (e-3).
Index Terms— 3GPP LTE, Convolutional interleaver,  MAP decoder, SOVA, Turbo decoder, VLSI ASIC.

3GPP Long Term Evolution (LTE) [1], which is a set  of enhancements to the 3G Universal Mobile Telecommunications System (UMTS) [2], has received tremendous attention recently and is considered to be a very promising 4G wireless technology. For example, Verizon Wireless has decided to deploy LTE in their next generation 4G evolution. One of the main advantages of 3GPP LTE is high throughput. For example, it provides a peak data rate of 326.4 Mbps for a 4×4 antenna system, and 172.8 Mbps for a 2×2 antenna system for every 20 MHz of spectrum. Furthermore, LTE-Advance [3], the further evolution of LTE, promises to provide up to 1 Gbps peak data rate. The channel coding scheme for LTE is Turbo coding [4]. The Turbo decoder is typically one of the major blocks in a LTE wireless receiver. Turbo decoders suffer from high decoding latency due to the iterative decoding process, the forward backward recursion in the maximum a posteriori (MAP) decoding algorithm and the interleaving/de-interleaving between iterations. Generally, the task of an interleaver is to permute the soft values generated by the MAP decoder and write them into random or pseudo-random positions.
In order to explain the proposed Turbo decoder architecture, the fundamentals of Turbo codes are briefly described in this section.

2.1 Turbo encoder structure

As shown in Fig. 1, the Turbo encoding scheme in the LTE standard is a parallel concatenated convolutional code with two 8-state constituent encoders and one convolutional interleaver [5]. The function of the convolutional interleaver is to take a block of N-bit data and produce a permutation of the input data block. From the coding theory perspective, the performance of a Turbo code depends critically on the interleaver structure [8]. The basic LTE Turbo coding rate is 1/3. It encodes an N-bit information data block in to a code word with 3N+12 data bits, where 12 tail bits are used for trellis termination. The initial value of the shift registers of the 8-state constituent encoders shall be all zeros when starting to encode the input information bits. LTE has defined 188 different block sizes.
The convolutional encoder can be represented as follows [6]:

• g0 = 1 + D + D2 + D3 + D6
• g1 = 1 + D2 + D3 + D5 + D6

The convolutional encoder basically multiplies the generator
Polynomials by the input bit string, as follows:

• A(x) = g0(x) * I(x) = a b c … g
• B(x) = g1(x) * I(x) = P Q R … V

Interleaving the two outputs from the convolutional encoder yields E(x) = aPbQcR … gV, which can also be written as:

E(x) = (a0 b0 c0 … g0) + (0P0Q0R … 0V) = A(x2) +x*B(x2)
Therefore, E(x) = A(x2) +x*B(x2) and A(x2)=g0 (x2) +I(x2) and  B(x2) = g1(x2) * I(x2), with the following.E(x) = g0(x2) * I(x2) + x * g1(x2) * I(x2)
        = I(x2) * (g0(x2) + x * g1(x2))
        = I(x2) * G(x)
 Where G(x) = g0(x2) + x * g1(x2)
i.e.G(x) =1 + x + x2 + x4 + x5 + x6 + x7 + x11 + x12 + x13.

2.2 Turbo Decoder Structure

The basic structure of a Turbo decoder is functionally illustrated in Fig.2. A turbo decoder consists of two maximum a posteriori (MAP) decoders separated by an interleaver that permutes the input sequence. The decoding is an iterative process in which the so-called extrinsic information is exchanged between MAP decoders. Each Turbo iteration is divided in to two half iterations. During the first half iteration, MAP decoder 1 is enabled. It receives the soft channel information (soft value Ls for the systematic bit and soft value Lp1 for the parity bit) and the a priori information La1 from the other constituent MAP decoder through deinterleaving to generate the extrinsic information Le1 at its output. Likewise, during the second half iteration, MAP decoder 2 is enabled, and it receives the soft channel information (soft value Ls for a permuted version of the systematic bit and soft value Lp 2 for the parity bit) and the a priori information La2 from MAP decoder1 through interleaving to generate the extrinsic information Le2 at its output. This iterative process repeats until the decoding has converged or the maximum number of iterations has been reached. 

2.3 Convolutional Interleaver

A convolutional interleaver [8] consists of N rows of shift registers, with different delay in each row. In general, each successive row has a delay which is J symbols duration higher than the previous row as shown in Fig. 3. The code word symbol from the encoder is fed into the array of shift registers, one code symbol to each row. With each new code word symbol the commutator switches to a new register and the new code symbol is shifted out to the channel. The i-th (1 ≤ i ≤ N-1) shift register has a length of (i-1)J stages where J = M/N and the last row has M-1 numbers of delay elements. The convolutional deinterleaver performs the inverse operation of the interleaver and differs in structure of the arrangement of delay elements. Zeroth row of interleaver becomes the N-1 row in the deinterleaver. 1st row of the former becomes N-2 row of later and so on.
In order to verify the Verilog HDL models for the interleaver and deinterleaver the authors have developed another top level Verilog HDL model, combining interleaver and deinterleaver [8]. The scrambled code words from the output of the interleaver is applied as input to the deinterleaver block along with clock as synchronization signal. It is observed in Fig 4 that the scrambled code word is converted into its original form at the output of the deinterleaver block.

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