Author Topic: A High Performance and Low Power Hardware Architecture for H.264 Transform Codin  (Read 1648 times)

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Author : Jubli Kashyap,Virendra Kumar Yadav
International Journal of Scientific & Engineering Research Volume 2, Issue 6, June-2011
ISSN 2229-5518
Download Full Paper : PDF

Abstractó In the search for ever better and faster video   compression standards H.264 was created. H.264 promises to be an excellent video format for use with a large range of applications and need for hardware acceleration of its very computationally intensive parts. To address this need, this paper proposes architecture for the discrete transform (DCT) and quantization blocks from H.264. The first set of architectures for the DCT and quantization were optimized for power, which resulted in transform and quantizer blocks that use 10.5623 mW Power. All of the designs were synthesized for Cadence BuildGate Synthesis CMOS technology, as well as the combined DCT and Quantization blocks went through comprehensive place and route flow.
  Index TermsóCMOS Technology,  DCT, H.264, JVT, ITU-T, SoC, Quantization, YUV System, Zero Shift.

1   INTRODUCTION                                                                      
Due to the remarkable progress in the development of products and services offering full-motion digital video, digital video coding currently has a significant economic impact on the computer, telecommunications, and imaging industry . This raises the need for an industry standard for compressed video representation with extremely increased coding efficiency and enhanced robustness to network environments. Since the early phases of the technology, international video coding standards have been the engines behind the commercial success of digital video compression.  ITU-T H.264/MPEG-4 (Part 10) Advanced Video Coding  (commonly referred as H.264/AVC) is the newest entry in the series of international video coding standards. It was
developed by the Joint Video Team (JVT), which was
formed to represent the cooperation between the ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Moving Picture Experts Group (MPEG) [3]-[5]. Compared to the currently existing standards, H.264 has many new features that makes it the most powerful and state-of-the-art standard . Network friendliness and good video quality at high and low bit rates are two important features that distinguish H.264 from other standards. The usual 8x8 DCT is the basic transformation in H.264. This eliminates any mismatch issues between the encoder  and the decoder.
The demand of multimedia communications on mobile and portable applications is growing nowadays. To real-ize multimedia communications, implementing a video compression standard is essential in any multimedia processing system-on-a-chip (SoC). There have been re-ports on the very large-scale integration (VLSI) implementation of MPEG-4 video recently. The emerging efficient H.264 or MPEG-4 Part 10 standard can greatly reduce the bandwidth and storage requirements for multimedia data. The VLSI implementation of H.264 is a challenge since an H.264 baseline decoder is approximately three times more complex than an H.263 baseline decode. Implementational flexibility is an important factor of concern for SoC designs. Since the traditional hardwired design is less flexible, the processor-based implementation is a preferred choice. VLSI implementation can be categorized into three types, hardwired, digital-signal-processor-based, and hybrid. To achieve higher performance with flexibility, the hybrid architecture has been proposed.

2 DESIGN REQUIREMENTS OF THE H.264 TRANSFORM

2.1 Discrete Cosine Transform

The DCT is conceptually similar to the DFT, except:
The DCT does a better job of concentrating energy into lower order coefficients than does the DFT for image data.
The DCT is purely real, the DFT is complex (magnitude and phase).The DCT is purely real, the DFT is complex (magnitude and phase).
A DCT operation on a block of pixels produces coeffi-cients that are similar to the frequency domain coefficients produced by a DFT operation. An N-point DCT has the same frequency resolution as and is closely related to a 2N-point DFT. The N frequencies of a 2N point DFT correspond to N points on the upper half of the unit circle in the complex frequency plane.
Assuming a periodic input, the magnitude of the DFT coefficients is spatially invariant (phase of the input does not matter). This is not true for the DCT. For most images, after transformation the majority of signal energy is carried by just a few of the low order DCT coefficients. These coefficients can be more finely quantized than the higher order coefficients. Many higher order coefficients may be quantized to 0 (this allows for very efficient run-level coding).

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