Author Topic: Low-Power 1-bit CMOS Full Adder Using Subthreshold Conduction Region  (Read 2270 times)

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Author : Vishal Sharma, Sanjay Kumar
International Journal of Scientific & Engineering Research Volume 2, Issue 6, June-2011
ISSN 2229-5518
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Abstract— In balancing the trade-off between power, area and performance, numerous efforts have been done. However, not much study has been done at the two extreme ends of the design spectrum, namely the ultra low-power with acceptable performance at one end (the main concern of this paper), and high performance with power within limit at the other. This paper is based on the exclusive use of subthreshold conduction currents to perform circuit operations, yielding a dramatic improvement in power consumption compared to traditional circuit design approaches. This improvement makes it feasible to design extreme low-power circuits with such an approach. The CMOS digital circuits for this work have been designed using standard TSMC 0.18 μm Technology.
Index Terms— Low-Power, Subthreshold Conduction Region, Full Adder.

1   Introduction                                                                      
IN most VLSI applications, arithmetic operations play an important role. Commonly used operations are addition, subtraction, multiplication and accumulation, and 1-bit Full Adder is the building block for most implementations of these operations. Obviously, enhancing the building block performance is critical for enhancing overall system performance [1] and in present, the power consumption has become a critical concern in today’s VLSI system design. The need for low-power VLSI systems arises from two main forces. First, with the steady growth of processing capacity per chip, large current has to be delivered and the heat due to large power consumption must be removed by proper cooling techniques. Second, battery life in portable electronic devices is limited. Low-power design directly leads to prolonged operation time in these portable devices [2].
Subthreshold circuit design provides an efficient solution to significantly reduce the power. So this work is based on subthreshold conduction principle to design a low-power 1-bit Full Adder. In subthreshold circuits, the supply voltage is reduced well below the threshold voltage of a transistor. Due to the quadratic reduction in power with respect to the supply voltage, subthreshold circuits are classified as ultra low-power circuits.
Specifically in application areas where performance can be sacrificed for low-power, subthreshold circuits are an ideal fit. Some of the applications include devices such as digital wrist watches, radio frequency identification (RFID), sensor nodes, pacemakers and battery operated devices such as, cellular phones [3].

2 Motivation of Power Reduction
Up until now, the power consumption has not been of great concern because of the availability of large packages and other cooling techniques having the capability of dissipating the generated heat. However, continuously increasing density as well as the size of the chips and systems might cause to difficulty in providing adequate cooling and hence, might either add significant cost to the system or provide a limit on the amount of the functionality that can be provided [4].
Another factor that fuels the need for low-power chips is the increased market demand for portable consumer electronics powered by batteries. For these high performance portable digital systems, running on batteries such as-laptops, cellular phones and personal digital assistants (PDAs), low-power consumption is a prime concern because it directly affects the performance by having effects on battery longevity.
Hence, low-power 1-bit Full Adder design has assumed great importance as an active and rapidly developing application in VLSI. Due to their extreme low-power consumption, subthrehsold design approaches are appealing for a widening class of applications which demand low-power consumption and can tolerate larger circuit delays.
3 Subthreshold Conduction For Low-Power VLSI Design
Digital subthreshold circuits are currently used for some low-power applications such as hearing aids, wrist watches, pacemaker and wireless communication systems [5]. In subthreshold circuit design, supply voltage must be scaled down below the threshold voltage. Therefore, the load capacitance is charged or discharged by the subthreshold leakage current. When the Adder circuits operate in the subthreshold region, they should have different performance characteristics than those of the Adders working in the strong inversion region [6]. In this paper, we will see the characteristics of a 1-bit Full Adder cell operating in subthreshold region of operation comparing it with the 1-bit Full Adder cell operating in strong inversion.
In traditional digital VLSI design, subthreshold region of operation is avoided, since it contributes toward leakage power consumption when the device is in stand-by. But the power can be reduced significantly by exclusively utilizing this subthreshold leakage current to implement circuits. This is achieved by actually setting the circuit power supply V_dd to a value less than or equal to V_th. The subthreshold current is exponentially related to gate voltage giving the exponential reduction in power consumption, but also an increase in circuit delay [7]. So, we use the circuits operating in subthreshold conduction region where the power is main concern and large delay can be tolerated.

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