Author Topic: Recurrent Neural Prediction Model for Digits Recognition  (Read 2506 times)

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Recurrent Neural Prediction Model for Digits Recognition
« on: December 13, 2011, 09:01:07 am »
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Author : Tellez Paola
International Journal of Scientific & Engineering Research Volume 2, Issue 11, November-2011
ISSN 2229-5518
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Abstractó It is often seen that the available knowledge base within an organisation influences the selection of the design platform. The two major contenders for signal processing hardware platforms are DSP processor and FPGA. DSP processor offers high compute intensive complete embedded product where as FPGA offers high flexibility to a System on Programmable Chip (SoPC) designer for proof of concept at formative stage of the system design leading to manufacturable prototype at a later stage before the final ASIC implementation. The constraint aware design brings forth many challenges in terms of cost, size, memory, performance and time to market.  The paper highlights the design cycle of finding the right platform after weighing the pros and cons of the design constraints and the design space exploration by way of a project based case study of a 3-D camera controller SoPC design on FPGA.
Index Termsó DSP, FPGA, SoPC, Camera, Embedded

1   INTRODUCTION                                                                    
 
Electronics systems in general can be categorized into two major systems; i.e., Personal Computer Systems and the rest are the Embedded Systems. The hardware platforms for embedded systems design fall into three electronic device families namely Microcontroller, DSP processor and FPGA. There are combinations of these entities available from chip vendors to suit a particular application. Few examples are DSPIC from Microchip combines DSP and Microcontroller, Actel offers Microcontroller and FPGA combination, and Xilinx announced FPGA with ARM hard processor.
 
DSP processors have DSP specific instructions with float-ing or fixed point computing capabilities. However to provide digital logic functionalities like timing signal generation, an extra programmable logic device such as CPLD or FPGA is required. On the other hand FPGA, having ocean of gates, are like temples without god, where a domain as demigod need to be installed by System on Programmable Chip designers. Em-bedding a Soft processor in FPGA to handle microcontroller like functionality along with the resident DSP specific primi-tives of FPGA makes it the most versatile among the design platforms.

The paper presents platform independent top-level design architecture of a 3-D camera controller and highlights the selection process of possible architectures based on DSP only, FPGA only and a heterogeneous combination of DSP and FPGA. The choice of the final architecture led to FPGA, deviating from the DSP processor, in spite of DSP being the natural choice of a hardcore DSP company with immense in-house knowledgebase on DSP tools and technologies. The project outsourcing company, who intended to design an ASIC for the 3-D camera controller, influenced the selection of the design architecture and the world knows that the FPGAs are the best prototype Pre-ASIC design platform.
The paper is organized as follows; 3-D camera system is introduced in Section 2, Section 3 covers System partitioning and architectures combination on DSP and FPGA. Section 4 covers benchmarking architectures against various constraints. Section 5 covers implementation of 3-D camera processor briefly. Concluding remark is given in Section 6 followed by reference in Section 7.

2 3-D CAMERA SYSTEM
A 3 Dimension camera system is based on Photon Mixer Device (PMD) [1][2][3][4] image sensor, which is used to cap-ture distance information of 3-D Image. It works on time of flight (ToF) principle of IR light generated by the IR LED source, the radiation reflected off the target and captured by the image sensor. Furthest the object from the light source, minimum is the reflection on the image sensor. The 3-D PMD sensor data is processed by the Digital Signal Processor to generate three image parameters i.e., amplitude, offset and phase. These image parameters are sent to host computer system over USB communication. The image parameters are analyzed and reconstructed on host computer for 3-D object rendering.

The 3-D camera system is based on two main components, namely light emitter and light detector. The system block diagram in Fig-1 shows LED array driven by LED driver, which constitute the light emitter section. Rest of the blocks constitute the light detector, comprising of sub-blocks, namely PMD image sensor, Sensor analog output signal conditioner, ADC, Sensor time and control signal generator, Digital Signal Processing, Sensor data storage memory, USB device driver and controller.  Besides these sub blocks the unit has lens and filter arrangement mounted on PMD sensor.

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