Design of Viterbi Decoder for noisy channel on FPGA
|
Full Text(PDF, 3000) PP.
|
|
Author(s) |
Ms. M.B.Mulik, Prof. U.L.Bombale, Prof. P.C.Bhaskar |
|
KEYWORDS |
wireless, low power, Viterbi Decoder, register exchange, memory less.
|
|
ABSTRACT |
The problem of survival memory management of a Viterbi Decoder (VD) was solved by introducing a pointer implementation for the register exchange (RE) method, where a pointer is assigned to each row of memory in the SMU. The content of the pointer which points to one row of memory is altered to point to another row of memory, instead of copying the contents of the first row to the second. In this paper, the one-pointer VD is proposed; if the initial state of the convolutional encoder is known, the entire survivor memory unit (SMU) is reduced to only one row. Because the decoded data are generated in the required order, even this row of memory is dispensable. Thus, the one-pointer architecture, referred to as memory less Viterbi Decoder (MLVD), reduces the power consumption of a traditional trace back (TB) VD by approximately 50 percent. A prototype of the MLVD with a one third convolutional code rate and a constraint length of nine is mapped into a Xilinx.
|
|
References |
|
[1] D. A. El-Dib and M. I. Elmasry, “Modified registerexchange
viterbi decoder for low-power wireless
communications,” IEEE Transactions on Circuits and
Systems I, vol. 51, no. 2, pp. 371-378, February 2004.
[2] A. Viterbi, “Error bounds for convolutional codes and
asymptotically optimum decoding algorithm,” IEEE
Transactions on Information theory, vol. It-13, no. 2, pp.
260–269, April 1967.
[3] G. Forney, “The viterbi algorithm,” Proceedings of the
IEEE, vol. 61, no. 3, pp. 268–278, March 1973.
[4] S. B. Wicker, Error Control Systems for Digital
Communication and Storage. Prentice Hall, 1995.
[5] J. H. et al, “Cdma mobile station modem asic,” IEEE
Journal of Solid- State Circuits, vol. 28, no. 3, pp. 253-
260 March 1993.
[6] I. Kang and A. W. Jr, “Low-power viterbi decoder for
cdma mobile terminals,” IEEE Journal of Solid-State
Circuits, vol. 33, no. 3, pp. 473- 482, March 1998.
[7] Inyup Kang, Member, IEEE, and Alan N. Willson Jr.
Fellow IEEE.”Low-Power Viterbi Decode for CDMA
mobile terminals” Ieee journal of solid-state circuits
, vol.33, no. 3, march 1998,
[8] James Tang and Esam Abdel-Raheem “High Speed
Viterbi Decoder Design and FPGA
Implementation” .Department of Electrical and
Computer Engineering , University of Windsor,
Ontario, Canada N9B 3P4.
[9] C. B. Shung et al., “Area-efficient architectures for the
Viterbi algorithm Part I: Theory,” IEEE Trans.
Commun., vol. 41, pp. 636–644, Apr. 1993.
[10] S.-S. Wang, “A state-reduction viterbi decoder for
convolutional codes with large constraint
lengths,” Master’s thesis, National Chiao Tung
University, Hsinchu, Taiwan, June, 2002
[11] H.-L. Lou, “Linear distances as branch metrics for
viterbi decoding of trellis codes,” Proc. IEEE
International Conference on Acoustics, Speech, and
Signal Processing, vol. 6, pp. 3267-3270, June 2000
[12] R. Henning and C. Chakrabarti, “Low-power
approach for decoding convolutional codes with
adaptive viterbi algorithm approximations, ”Proc.
IEEE International Symposium on Lower Power
Electronics and Design, pp. 68-71, August 2002.
|
|
|