Design and Performance Analysis of a 3GPP LTE/LTE-Advance Turbo Decoder using Software Reference Models
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| Author(s) |
|Lohith Kumar H G, Manjunatha K N, Prof.Cyril Prasanna Raj P, Suma M S, C K Raju|
| KEYWORDS |
3GPP LTE, Convolutional interleaver, MAP decoder, SOVA, Turbo decoder, VLSI ASIC.
This paper presents the design and development of an efficient VLSI architecture for 3GPP advanced Turbo decoder by utilizing the convolutional interleaver. The high-throughput 3GPP Advance Turbo code requires turbo decoder architecture. Interleaver is known to be the main obstacle to the decoder implementation and introduces latency, due to the collisions it introduces in accesses to memory. In this paper, we propose a lowcomplexity soft Input Soft Output (SISO) turbo decoder for memory architecture to enable the Turbo decoding that achieves minimum latency. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed Turbo decoder has been modeled using Simulink; various test cases are used to estimate the performances. The results are analyzed and achieved 50% reduction in computation time along with reduced BER (e-3).
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