Inte rnatio nal Jo urnal o f Sc ie ntific & Eng inee ring Re se arc h, Vo lume 3, Issue 2, February -2012 1

ISS N 2229-5518

VLSI Design of Low Power Booth Multiplier

Nishat Bano

2 and modif ied radix 4 Booth multipliers. Experimenta l results demonstrate that the modif ied radix 4 Booth multiplier has 22.9% pow er reduction than the conventional radix 2 Booth Multiplier.

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Continuous advances of micr oelectr onic technologies make better use of ener gy, encode data mor e effectively, transmit information mor e r eliable, etc. Particular ly, many of these technologies addr ess low-pow er consumption to meet the r equir ements of var ious portable applications [5]. In these application systems, a multiplier is a fundamental ar ithmetic unit and widely used in circuits.

VHDL is one of the common techniques for the

digital system emer gent pr ocess. The technique is done by

pr ogram using certain softwar e which per forms simulation and examination of the designed system. The designer only needs to descr ibe his digital circuit design in textual form

which can r emove w ithout the effort to alter the har dwar e. VHDL is mor e pr eferr ed because this technique can r educe cost and time, easy to tr oubleshoot, portable, a lot of platform softwar e support the VHDL function and high r efer ences availability. All the pr ocesses will be running using Xilinx ISE 8.2i softwar e which means the pr ocess is simulated only without any hardwar e implementation.

Multiplication is a fundamental operation

in most signal pr ocessing algor ithms. Multiplier s have lar ge ar ea, long latency and consume consider able pow er . Ther efor e low-pow er multiplier design has been an

impor tant part in low- pow er VLSI system design [6].

Fast multiplier s ar e essential par ts of digital signal pr ocessing systems. The speed of multiplier oper ation is of gr eat importance in digital signal pr ocessing as well as in the general pur pose pr ocessors today. The basic multiplication pr inciple is two fold i.e., evaluation of partial pr oducts and accumulation of the shifted partial pr oducts.

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*Nishat Bano is currently pursuing masters degree program in*

Digital Systems in Madan Mohan Malaviya Engineering College,

Gorakhpur, India. E-mail: nishat_rizvi20@yahoo.co.in

Booth algorithm pr ovides a pr ocedur e for multiplying binary integers in signed-2’s complement r epr esentation [1]. Accor ding to the multiplication pr ocedur e, strings of 0’s in the multiplier r equir e no addition but just shifting and a string of 1’s in the multiplier fr om bit w eight 2 k to w eight

2m can be tr eated as 2k+ 1 - 2m.

Booth algor ithm involves r ecoding the multiplier

first. In the r ecoded for mat, each bit in the multiplier can take any of the thr ee values: 0, 1 and -1.Suppose w e want to multiply a number by 01110 (in decimal 14). This number can be consider ed as the differ ence betw een 10000 (in decimal 16) and 00010 (in decimal 2). The multiplication by

01110 can be achieved by summing up the follow ing

pr oducts:

24 times the multiplicand(24 = 16)

2’s complement of 21 times the multiplicand (2 1 =

2).

In a standar d multiplication, thr ee additions ar e r equir ed due to the string of thr ee 1’s.This can b e r eplaced by one addition and one subtraction. The above r equir ement is identified by r ecoding of the multiplier

01110 using the follow ing r ules summar ized in table 1.

Qn | Qn+1 | Re coded bits | Operation performed |

0 | 0 | 0 | Shift |

0 | 1 | +1 | Add M |

1 | 0 | -1 | Subtr act M |

1 | 1 | 0 | Shift |

To generate r ecoded multiplier for radix-2, following steps ar e to be per formed:

IJSER © 2012

Inte rnatio nal Jo urnal o f Sc ie ntific & Eng inee ring Re se arc h, Vo lume 3, Issue 2, February -2012 2

ISS N 2229-5518

Append the given multiplier w ith a zer o to the LSB

side

Make gr oup of tw o bits in the overlapped way

Recode the number using the above table.

Consider an example which has the 8 bit multiplicand as

11011001 and multiplier as 011100010. Multiplicand 1 1 0 1 1 0 0 1

Multiplier 0 1 1 1 0 0 0 10

Recoded mult iplier +1 0 0 -10 0+1-1

0 0 0 1 0 0 1 1 1

1 1 1 0 1 1 0 0 1

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0

0 0 0 1 0 0 1 1 1

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0

1 1 1 0 1 1 0 0 1

Pr oduct 0000001001001001

One of the solutions of r ealizing high speed multiplier s is to enhance parallelism which helps to decr ease the number of subsequent calculation stages. The original version of the Booth algor ithm (Radix-2) had tw o drawbacks. They ar e:

(i) The number of add subtract operations and the

number of shift operations becomes var iable and becomes inconvenient in designing parallel multiplier s.

(ii) The algor ithm becomes inefficient when ther e ar e

isolated 1’s. These prob lems ar e over come by

using modified Radix 4.

Booth algor ithm which scans strings of thr ee bits is given below:

1) Extend the sign bit 1 position if necessary to ensur e that n is even.

2) Append a 0 to the r ight of the LSB of the multiplier .

3) Accor ding to the value of each vector , each Partial

Pr oduct will b e 0, +M,-M, +2M or -2M.

The negative values of B ar e made by takin g the 2’s complement and in this paper Carry-look-ahead (CLA) fast adders ar e used. The multiplication of M is done by shifting M by one bit to the left. Thus, in any case, in designing n-bit parallel multiplier , only n/2 par tial pr oducts ar e pr oduced.

The partial pr oducts ar e calculated according to the follow ing r ule

Zn= -2×Bn+1 + Bn +Bn-1 (1)

wher e B is the multiplier .

Consider example for r adix 4: Multiplicand 1 0 0 0 0 0 0 1

Multiplier 0 1 1 1 1 1 1 0 0

+2 0 0 -2

0000000011111110

00000000000000

000000000000

1100000010

Pr oduct __1100000101111110__

W e evaluate the per formance of conventional and modified booth multiplier s and implement them on FPGA. For Design Entr y, we used ModelSim 6.5c and design w ith VHDL. In or der to get the pow er r eport and delay r eport w e synthesize these multiplier s using Xilinx ISE 8.2i.

The comp ar ison of

synth esis

r eport for conve ntion al and modif ied Booth multi

IJSER © 2012

Inte rnatio nal Jo urnal o f Sc ie ntific & Eng inee ring Re se arc h, Vo lume 3, Issue 2, February -2012 3

ISS N 2229-5518

pliers is given in Table 3.

Multiplier Type | Radix 2 | Radix 4 |

Device and family | Spartan 2 | Spartan 2 |

No. of slices | 77 | 72 |

No. of LUTs | 140 | 129 |

No. of Bonded I/O | 32 | 32 |

Delay(ns) | 27.110 | 26.103 |

Power Dissipation(mW) | 15 | 11 |

In this paper , the conventional and modified b ooth multiplier s ar e designed using VHDL. The delay and pow er dissipation of modified r adix 4 Booth multiplier is less as compar ed to the conventional one. When implemented on FPGA, it is found that the radix 4 booth multiplier consumes 22.9% less pow er than conventional radix 2 multiplier . Also estimated delay is less for radix 4 multiplier .

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