ability. From which two procedures were proposed in [6] and
[7] to decrease testing power using changing task concept.
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Testing Of Digital Circuits with Conserved Power
Utilization: Jumbled Test Sequence Approach
Y. Sreenivasula Goud1 Dr.B.K.Madhavi2
Lately, energy usage and power dissipation have attained substantial focus in VLSI circuit design. Several factors have led to this trend. With the arrival of mobile products, low energy consumption has become one of many leading design goals in order to lengthen battery life. Moreover the amount of energy consumed by the circuit is directly reflected in its heat dissipation, and requires costly packaging and chilling practices, which raises system cost [9]. Additionally, as power consumption increases, signal reliability gets impacted negatively because of electro migration. When the circuit is examined with pseudorandom patterns, successive input test vectors are statistically separate which leads to increased switching activity within the signal under test. The average power usage during screening is considerably greater than normal way of operation, because in CMOS circuits energy is mostly consumed by signal changeover. The earlier work of this paper was based in the Hamming Distance between two successive test vectors. The test vectors are reordered so that the complete hamming distance for that entire test set is minimal. This Hamming Distance approach is dependent on the notion the internal switching activity is more or less depending in the distance at the feedback of the signal. This theory isn't accurate for all the circuits and also the switching activity is depending on the logic gates which are utilized to assemble the circuit. In this paper a new method is suggested in which changing action of the routine is considered rather hamming Space for reordering of test vectors. The test energy obtained by utilizing the reordered test set is seen as ideal test strength.
More methods are mentioned in literature for reducing testing
Email: bkmadhavi2009@gmail.com, ph: +91-9393810658
Both the strategies are derived from Genetic Algorithm approach in which the fault coverage is transformed while reordering is carried out. This will definitely degrade the operation of fault simulator algorithm or Automatic Test Pattern Generator (ATPG).The proposed method is dependent upon Graph Theory method where the fault coverage isn't transformed and important improvement in minimizing switching activity during screening is realized.
The Power dissipation in CMOS technology [8,10] can be classified into static and dynamic. Fixed dissipation is because of leakage current that has small magnitude in digital CMOS circuits. Therefore, for such circuits, the powerful dissipation is the dominant term. Energetic dissipation occurs in a node once it switches from one logic level to some other logic stage. Dynamic dissipation is broken into two parts caused by charge / discharge current and short-circuits current. The later is caused by switching activity of transistors during 0 → 1 or from 1 → 0 transitions. The charge/discharge present is the present that charges and discharges the capacitive load on the production of a gate during 0 → 1 or from 1 → 0 transitions and in common, dominates energetic power dissipation [10,3]. The dynamic power dissipation (PD) in the route is given by (1)
ability. From which two procedures were proposed in [6] and
[7] to decrease testing power using changing task concept.
PD = 1
2
jn CL ( j)s( j)Vdd
(1)
Author 1: Professor & Head of ECE, Ravindra College of Engineering for
where CL ( j) is the load capacitance at line j of the Circuit
women, Kurnool , A.P, India.
Under Test (CUT),
s( j) is the regularity of switching of the
Email : ysgoud18@yahoo.co.in , ph: +91-9951860531
line j, and Vdd
is the power Supply voltage. Other quantities
Author2: Professor in ECE Department, Geethanjali College of Engineering and Technology, Cheeryal(V),Keesara(MDL),RR Dist..
organism constant for a given course, test vector set generated
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ISSN 2229-5518
to diminish the frequency of control at circuit lines during test submission will minimize the heat debauchery during testing.
In this thesis we present a new method for power
the vector set generated.
R , is a set to store prepared test vector sequence.
Q is a set to store T − R .
reduction in testing of digital circuits
Step 1: Select a test vector x such that minimum. Add x to set R .
swa _ init [x ] is
The power dissipation during testing [4] is minimized by
Step 2: Select a test vector Ymin
minimum.
such that swa [ x][ ymin ] is
lowering the number of transition in the circuit. Generally test
Step 3: Add Ymin
to R. Q → T − R .
X min ← Ymin .
vectors come in arbitrary and thus it is needed so the
Step 4: From
swa [Xmin ][j] where j varies as in Q , find
switching action between consecutive test vectors is minimal
to arrange the sequence of incidence of test vectors.
The problem of minimizing switching power is solved by data theory using Hamiltonian path [5] method. The problem is formulated by contemplating the evaluation vector as node and changing activity between them as border expense of the chart. Here the Hamiltonian path is really a path with minimal total edge cost and all nodes. Reordering formula [1] is used to assemble the Hamiltonian path, which is resultant reordered test vector set whose absolute switching activity is minimum. Now the path developed from the algorithm is reordered test vector series which offers less number of transitions in the routine which subsequently leads to decreased power dissipation in the Circuit Under Test (CUT) throughout screening [5]. The Algorithm to decrease the Switching activity during testing is following.
minimum value as swa [ X min ][Ymin ] . Go to step 3.
Step 5: If Q is not empty go to step 3 otherwise go to step 6.
Step 6: Stop the process and find the total switching movement of the circuit.
Finally set R will have reordered test vector succession with minimum switching movement in the CUT . When the reordered test vectors are practical the total switching activity of the circuit is designed by the given equation,
n −1
SWAtotal = swa _ init[R[1]] + ∑ swa[R[i]][Ri + 1]
i =1
Where n = total number of test vectors.
R [i] = ith positional test vector number stored in the
R .
1. Mull over a digital circuit with p inputs and q outputs.
2. Generate all the test vectors to observe the entire single stuck at faults [4] of the course. The analysis vector may be having don’t care. Let the digit of test vectors be n.
3. Find the internal switching action between each and every test vector by affect them in the CUT and load the
identical in array swa of size n x n. Let swa [i][ j] be the
array component that gives switching movement between ith
set
The aforementioned procedure is illustrated with simple ISCAS85 benchmark circuit c17 to show the effectiveness of the suggested system. The test vector set that employed to detect the whole single stuck at faults is given in Table 1. This is created by ATPG tool called ATALANTA. The vectors are displayed by the sequence of incident for the interest of
convenience. The switching activity arrays swa [ ] [ ] and
swa _ init [ ]are constructed by using the evaluation set in
CUT . This is provided as in (2) and (3). On application of
and
jth test vector.
4. Find the internal switching movement of every test
reordering algorithm to these matrices, the reordered test
vectors sequence is created with minimum switching action.
vector by applying them in the CUT independently and load the same in array swa _ init of size n x 1 . Let swa _ init [i]
be the array component that gives initial switching activity when ith test vector is applied.
5. Apply reordering algorithm to find the reordered test vector succession with minimum total switching activity.
The various parameters used in the algorithms are as follows:
t1 , t 2 , ... t n , be n test vectors with m bits each.
Table.1 Test vectors for c17 circuit
T = {1, 2,. k ... n} , where k represents k th position in
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ISSN 2229-5518
swa [i] [ j] =
{[(t1, t 2) = 7, (t1, t 3) = 7, (t1, t 4) = 7, (t1, t 5) = 6, (t1, t 6) = 7]
[(t 2, t1) = 5, (t 2, t 3) = 8, (t 2, t 4) = 4, (t 2, t 5) = 9, (t 2, t 6) = 8] [(t 3, t1) = 7, (t 3, t 2) = 14, (t 3, t 4) = 10, (t 3, t 5) = 7, (t 3, t 6) = 4] [(t 4, t1) = 7, (t 4, t 2) = 4, (t 4, t 3) = 4, (t 4, t 5) = 7, (t 4, t 6) = 8] [(t 5, t1) = 6, (t 5, t 2) = 7, (t 5, t 3) = 7, (t 5, t 4) = 7, (t 5, t 6) = 5]
[(t 6, t1) = 7, (t 6, t 2) = 10, (t 6, t 3) = 4, (t 6, t 4) = 12, (t 6, t 5) = 5]}
swa _ init [i]=
[t1 = 15, t 2 = 22, t3 = 0, t 4 = 18, t5 = 15, t 6 = 12]
After applying the test sequence jumbling approach, the
jumbled test sequence is specified as t3 - t6 - t5 - t1 - t2 - t4
whose total switching movement is 26. The proposed method
reduces the switching activity from original value 49 to final
value 26, which shows that 47% of decrease in switching
activity is attained
The algorithm is examined and employed with ISCAS 85 benchmark circuits. The results are shown within the Table 2 for the proposed work and its previous work which was centered on switching activity [11]. For every single circuit, an array of test vectors to detect single stuck at faults are created. Total switching activity is calculated for every single test vector and also the switching activity matrix is obtained. The switching action matrix is placed on the reordering algorithm. The total switching action of the routine after reordering is shown in the "projected work” by swa[i][ j] . The effects of projected work are compared with previous work [2] [11] and their percent improvement is shown in last two columns of the resultant table. The results shown in these experiments are that switching activity is reduced up to 72% for the benchmark circuit c1355 . Thus the reduction in switching task reduces the testing power in combinational circuit.
Within this paper a strategy is proposed for decreasing the power dissipation during testing of combinational circuit. The proposed jumbled test sequence approach algorithm lessens the switching activity by reordering the test vectors, since the
80% of the complete power dissipation in CMOS circuits is a result of the switching activity. The algorithm is created using graph theory model and implemented by C language and Hardware Description Language (HDL) simulation programs. The functionality of the algorithm is tested with ISCAS bench mark circuits. Experimental results demonstrate that new approach reduces switching activity up to 72% when the test vectors generated by the proposed algorithm are utilized during test phase. Thus there's a decrease in power
dissipation during test phase. The low power design in VLSI Circuits make real demands for the test power optimization approaches of better optimization effect and time saving.
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