Leakage Power Reduction using Multi Threshold Voltage CMOS Technique


Sangeeta Parshionikar, Dr. Deepak V. Bhoir, Sapna Prabhu


Abstract— In deep sub–micron technology, standby leakage power dissipation has emerged as major design consideration. In this paper, multi threshold voltage CMOS technique for reducing leakage power is proposed. In this technique, the resistance of the path from Vdd to ground is increased, so that significant reduction in static power is achieved with little increase in delay. This work analyses the leakage power and delay of NAND gate and the same can extended to any complex digital implementation. The results are also compared with stacking technique. The circuits are simulated with MOSFET models of level 54 in 90 nm, 45nm and 32nm process technology.


Index Terms— Leakage power, MTCMOS, static power, stacking, sub threshold current, threshold voltage


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  1. INTRODUCTION

    A

    s technology scales down to the deep-submicron tech- nology, standby leakage power increases exponentially with the reduction of the supply voltage (Vdd) and the

    threshold voltage (Vth ). The advances in technology enable us to achieve higher density and performance at the same time results in increase in power consumption. In past day’s tech- nology the magnitude of leakage current was low and usually neglected. In current trends, the supply voltage is being scaled down to reduce dynamic power. The threshold voltage also follows the same scaling trend in order to satisfy the high speed requirements.

    This decrease of threshold voltages brings an exponential in- crease in sub-threshold currents [1]. Sub-threshold leakage is the weak inversion current between source and drain of MOS transistor observed when the gate voltage is less than the threshold voltage. Since the leakage current of the transistors determines the static power of a CMOS circuit, the increase in sub-threshold current increases the leakage power consump- tion of the circuit. Thus the total power consumption of the circuit is increased.

    Consequently, power dissipation is becoming recognized as

    a top priority issue for VLSI circuit design. Leakage power

    makes up to 50% of the total power consumption in today’s

    high performance microprocessors [2]. Therefore leakage

    power reduction becomes the key to a low power VLSI design.

    Leakage power dissipation is the power dissipated by the cir-

    cuit when it is in sleep mode or standby mode. Leakage pow-

    er is given by equation 1 and the propagation delay (Tpd) of a

    circuit is given by equation 2.


    Pleak = Ileak * Vdd (1)

    Tpd Vdd / (Vdd-Vth )2 (2)

    Where Ileak is the leakage current that flows in a transistor

    when it is in off state, Vdd is the supply voltage, Vth is the

    threshold voltage of the transistor. This power dominates dy-

    namic power especially in deep submicron circuits and also in

    circuits that remains in idle mode for a long time such as cell

    phones. In all such applications, it is important to prolong the

    battery life as much as possible and now with growing trend


    towards portable computing and wireless communication, power dissipation has become one of most critical factor in continued development of micro-electronic technology. There- fore the focus is on the reduction of leakage power dissipation.

    The rest of the paper is organized as follows, in Section 2, a review of the related work is presented. In Section 3, the pro- posed work on a leakage reduction for combinational NAND logic gate is presented, which is followed by the simulation results and conclusions in Sections 4 and 5, respectively.


  2. RELATED WORK

    High leakage current in deep-submicron technology is becom- ing a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. This section reviews different ap- proaches for leakage current reduction techniques. All these techniques are effective in reducing leakage power and ulti- mately all come down to a fundamental set of concepts: dissi- pation is reduced by lowering supply voltage, voltage swing, physical capacitance, switching activity or by introduction of a high resistance path between Vdd and ground.

    In self-adjustable voltage level circuit, the output voltage of the circuit is applied to any load circuit [3]. During the active mode (when SL=0), this circuit supplies maximum supply voltage to the load circuit so that the load circuit can operate quickly. During the standby mode, it provides slightly lower supply voltage to the load circuit through the weakly ON transistors. When drain to source voltage is decreased, the drain induced barrier-lowering (DIBL) effect is decreased and this in turn increases the threshold voltage Vth of NMOS tran- sistors. Consequently the sub threshold leakage current of the OFF MOSFETs decreases, so leakage power is minimized, while data are retained.


    A technique for leakage power control is Power gating [4], which turns off the devices by cutting off their supply voltage. This technique uses additional transistors (sleep), which are inserted in series between the power supply and pull-up net- work (PMOS) and/or between pull-down (NMOS) network and ground to reduce the standby leakage currents. The sleep


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    transistors are turned on when circuit are in active mode and turned off when circuits are in standby mode.

    The input vector method makes use of dependence of leak- age current on the input vector to gate [5]. Additional control logic is used to put the circuit in a low-leakage standby state when it is idle and restored to its original state when reactivat- ed. Upon reactivation, the circuit no longer retains the original state information before going into low-leakage standby state. Thus, to retain original state information, it requires special latches thereby increasing the area of circuit by about five times in worst cases.

    In dual threshold voltage CMOS technique, transistors of different threshold voltages are used. Low threshold voltage transistors are used for the gates on the critical path to main- tain the performance, while high threshold voltage transistors are used for the gates on the non-critical path for reduction of the leakage current.


  3. PROPOSED LEAKAGE REDUCTION TECHNIQUES

    1. MTCMOS Technique

      The multi-threshold voltage CMOS (MTCMOS) technique is a kind of power gating technique which uses high threshold transistor as a sleep transistor and low threshold voltage tran- sistors are used to implement the logic [7]. Multi-Threshold CMOS (MTCMOS) is an effective circuit-level methodology that improves the performance in the active mode and saves leakage power during the standby mode. The basic principle of the MTCMOS technique is to use low Vth transistors to de- sign the logic gates where the switching speed is important , while the high Vth transistors also called sleep transistors are used to effectively isolate the logic gates in standby state. The sleep transistors offer the high resistance between supply and ground and limit the leakage dissipation.

      Fig. 3.1(a) shows the basic circuit of MTCMOS. The sleep transistor (ST) in MTCMOS circuit is controlled by a sleep con- trol signal. During the standby mode (sleep=1), the ST is off. This causes the leakage current of the logic block to be limited to that of the ST. Due to the high Vth of ST, the total leakage of the circuit is minimized. On the other hand, in the active mode (sleep=0), the ST is turned on and the real ground line (GND) is directly connected to the virtual ground line (VGND). Con- sequently, the low Vth logic gates operate normally at a high speed. In the active mode, the sleep transistor works as a resis- tor as shown in Fig. 3.1(b)

      Thus, the introduction of sleep transistor increases the re-

      sistance of the path from Vdd to ground during standby mode

      of operation resulting in reduction of leakage current.


      Figure 3.1: Block diagram of MTCMOS circuit structure


      image

      Figure 3.1: Block diagram of MTCMOS circuit structure


    2. Transistor Stacking

      The leakage current flowing through a stack of series connect- ed transistors reduces when more than one transistor of the stack is turned OFF. This effect is known as the “Stacking Ef- fect”.

      Sub threshold leakage is exponentially related to the threshold voltage of the device and the threshold voltage changes due to body effect. From these two facts, the sub threshold leakage in the device can reduced by stacking two or more transistors serially. This is because each transistor in the stack induces a slight reverse bias between the gate and source of the transis- tor right below it, and this increases the threshold voltage of the bottom transistor making it more resistant to leakage [1]. Therefore in Fig. 3.2, transistor T2 leaks less current than tran- sistor T1 and T3 leaks less than T2. Hence the total leakage current through the transistors T1, T2 and T3 is decreased as it flows from Vdd to Gnd. So Ileak1 is less than Ileak2.


      image


      Figure 3.2: Transistor Stacking Effect


  4. SIMULATION AND RESULT

    The transistor multi – threshold CMOS and sTACKING tech- niques were implemented and tested on set of combinational circuits. NAND circuits are implemented and net lists are simulated using Synopsys HSPICE. The implementation of NAND using both the techniques is shown in figure 4.2 and figure 4.3 respectively. Conventional NAND circuit is shown in figure 4.1. All circuits were simulated at a temperature of 25°C. Their leakage power was measured in the standby mode of operation.


    image



    Figure 4.1: Conventional CMOS NAND Gate

    Figure 4.1: Conventional CMOS NAND Gate


    image

    Figure 4.2: Stacked NMOS Transistor NAND


    The Berkeley Predictive Technology Models (BPTM) contained process parameters and values for both standard threshold voltage and high threshold voltage devices [10]. The net lists of combinational logic gates are modified with respect to the Berkeley Predictive Technology Models. The modified net lists are also simulated using Synopsys HSPICE for power meas- urements.


    image


    Figure 4.3: MTCMOS NAND Gate


    The proposed methods provide exact logic levels and leak- age savings as the process technology shrinks. The leakage power measurements are made for the CMOS NAND using 90nm, 45nm and 32nm process technology.


    Tables I show the simulation results of NAND circuit for three different process technologies.

    From the table I, it is clear that the proposed MTCMOS technique yield more percentage reduction in standby power compared to the stacking technique.


    Table I

    Standby Leakage power (W) for NAND circuit


    Process Tech- nology


    Base case

    Transistor Stacking


    MTCMOS

    90n

    1.11E-12

    0.69E-12

    0.531E-12

    45n

    4.66E-09

    1.19E-09

    0.073E-09

    32n

    13.03E-06

    5.918E-06

    0.066E-06


    The proposed techniques achieve significant reduction in standby leakage power with increase in propogation delay. Minimal additional circuitry is used to modify the original logic design to force the combinational logic into a low- leakage state during both active and idle mode of operations. Since the power and delay are inter related, increase in propo- gation delay is minimum. The same is shown in figure 4.5 for NAND gate.


    image

    Figure 4.4: Total Leakage Power vs. Process Technology


    image


    Figure 4.5: Propogation delay for NAND gate


  5. CONCLUSION

Scaling down of the supply voltage and threshold voltage along with CMOS technology feature size for achieving high performance has largely contributed to the increase in standby leakage power dissipation. In this paper, for reducing leakage power efficient technique such as Multi – Threshold voltage CMOS is proposed. The digital circuit NAND gate is imple- mented with leakage reduction techniques. The leakage power of all the designs decrease when reduction techniques are ap- plied.

The percentage reduction of leakage power is more with the MTCMOS technique compared to the Stacking technique.


REFERENCES

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[6] Mohab Anis, Member, IEEE, Shawki Areibi, Member, IEEE, and Mohamed Elmasry, “Design and Optimization of Multithreshold CMOS (MTCMOS) Circuits”, IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, Vol. 22, No. 10, October 2003.


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[8] Deeprose Subedi and Eugene John “Stand-By Leakage Power Re- duction In Nanoscale Static Cmos Vlsi Multiplier Circuits Using Self Adjustable Voltage Level Circuit”, International Journal of VLSI de- sign & Communication Systems (VLSICS) Vol.3, No.5, October 2012.


[9] International Technology Roadmap for Semiconductors:

www.itrs.net/Links/2005ITRS/Design 2005.pdf.

[10] “Berkeley predictive technology model.” http://wwwdevice.eecs.berkeley.edu/~ptm.