International Journal of Scientific & Engineering Research Volume 2, Issue 10, Oct-2011 1

ISSN 2229-5518

Dynamic Response of Jospephson Resistive

Logic (DCI) GATE

K.Srinivas and J. C. Biswas

ABSTRACT ----- In this paper a thorough investigation of resistive logic gate DCI has been made. The current equations of this gate at each stage have been deduced. The dynamic response of this DCI gat e has been obtained by the computer-simulation. Our concept of turn-on delay has been introduced. The effect of overdrive current on turn-on delay for resistive logic gate has been shown. This will provide a better understanding of switching dynamics of the DCI logic gat e. Further, we have shown the effect of overdrive current on this logic gat e.

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1. INTRODUCTION

Two attractive features of SQUID devices for logic applications are isolation and serially connected fan-out. The isolation is provided by the transformer coupling between the SQUID and the input. The isolation is not perfect in the sense that a noise pulse (typically 5 percent) is fed back into the control line when the SQUID switches to the non-zero voltage. The other advantage is the serial fan-out capability by which the control lines of many load devices can be connected in series with a single output line.
The main drawbacks of SQUID devices for logic application are relatively large device area and high sensitivity to stray magnetic fields. In SQUID 80% of the area is occupied by the transformer [1]. Further, the high sensitivity to stray magnetic field requires that the SQUID based logic circuits be well shielded from the stray magnetic fields.
The resistive logic gates such as JAWS (Josephson Auto- Weber System) [2], DCI (Direct Coupled Isolation) [3] and RCJL (Resistor Coupled Josephson Logic) [4] are chosen because the gate logic delay in this case would consist of the turn-on delay, switching delay and propagation delay, but not the crossing delay as in the case of magnetically coupled logic gates. Further, these resistive logic gates do not have a factor of limiting the size very seriously. So, the gate propagation delay can be made sufficiently small. Therefore, the small time constant of the Josephson junction can be directly attained to these gates.
It has been considered by the earlier workers [5] that the turn-on delay of a logic gate is the time taken for the logic gate to obtain 2% of the output current to the load. This consideration seems to be orbitrary.

_ _ _ _ _ _

1. DEPARTMENT OF PHYSICS, GMR INSTITUTE OF TECHNOLOGY, RAJAM-532127,A.P., INDIA, Email : srinkura@gmail.com srinivas.k@gmrit.org

2. DEPARTMENT OF ELECTRONICS AND ELECTRICAL COMMUNICATION ENGINEERING, INDIAN INSTITUTE OF TECHNOLOGY , KHARAGPUR-721302 INDIA.

Due to this fact, in the present paper we have made a thorough investigation of the resistive logic gates. Our concept of turn-on delay [6] has been introduced which will be able to remove the confusion in critically ascertaining the switching speed of these logic gates. Further, the effect of overdrive current on these resistive logic gates has been studied.

2. DCI (DIRECT COUPLED ISOLATION)

This was proposed by Gheewala et al [3]. Here the J
osephson junction is used just a so called "diode" junction
- connecting the input signal to logic device to provide
isolation.
It consists of two Josephson junctions J1 and J2 as
shown in Fig.1. The junctions J1 has a critical current Io
and junction capacitance Cj, and the junction J2 has a
critical current 2 Io and the junction capacitance 2Cj. The
resistances of R1 and R2 are r and r/2 respectively. The
DCI gate is biased in the superconducting state by the
injection of the input current Iin. The junction J2 plays the
role of the current-summing junction in this gate.
When the input signal Iin is directly injected to this
DCI gate, it will add to the bias current in junction
J2 and substract from the bias in junction J1. The junction
J2 is a current-summing junction which switches first to
non-zero voltage state. This makes J2 highly resistive,
steering most of the signal and the gate current to ground through the resistor R1 (RL >> R1). The gate current Ig is selected to be sufficient to then switch J1 to the non-zero voltage state. With both J1 and J2 in the high-resistance state, the gate current is steered to the RL and signal current to ground via the resistor R1. The high-resistance of J1 prevents gate current from feeding back into the input signal line and thus provides isolation. However, the isolation is not perfect and a small amount of current (typically 3-5 percent) is fed back into the input line.
The above DCI gate can be modified or converted to a JAWS gate (as shown Fig.2). Here two differences are there between DCI and JAWS gates, one is the Ioff current is absent for DCI gate and the other one is that the extra resistor R2 is connected in series with the junction J2.
According to Fig.2 the current equations at each statge of the DCI gate can be written as:

International Journal of Scientific & Engineering Research Volume 2, Issue 10, Oct-2011 2

ISSN 2229-5518

(Note : Here the effect of subgap quasiparticle resistance
Rj has been neglected since Ri >> r, rL). (a) Static case

At t  0, Va

 Vb  0



d a

 db

 i3  i4  0

After using the above conditions in Eqns.(6.3.1) and
(6.3.2) we obtain,
Fig.1 Circuit configuration of the resistive DCI logic

g  2 sin

I o

 I in

I o

---- (I)
gate with threshold characteristics
Egn.(I) describes the static behaviour of DCI gate. A static
curve between 1g/Io and Iin/Io will give the operating margin and gain margins of the DCI gate.
(b) Dynamic case
Eqn. (1) can be written as

i  2 I

sin 

 2 C

a o

1 o

d 2

a j dt 2 2



dt 2



o C j

[ i1  2 I o sin  a ]

---- (8)
Fig. 2 Circuit configuration of the resistive DCI logic
Similarly. Egn.(2) can be written as,

gate with current indication at each stage of the logic

d b

 2 

[ i1

 i2

gate.

dt 2

o C j 2

i1 

2 I o

sin  a

 2C j

dVa

---- (1)

 2 I o sin  a

 I o sin ( a

b ) ]

---- (9)
Further, from Eqns. (6) and (7) we get,

i2  I o sin ( a

  b )  C j

(Va  Vb )

---- (2)

i1  I g

 I in

 (i3  i4 )

i2   I in

 i3

i3 

---- (3)
Substituting the above values il and i2 in Egns.(8) and (9)
we obtain,

i4 

---- (4)

d 2

dt 2

 

o C j

[ I g

 I in

 2 I o

i  Va

o d b

o d a

 d

---- (5)

sin  a

2  R1



dt 2  rL

]

--- (II)

Va  2 dt

; Vb  2 dt

----(6)

and

d  b

 2 

I g 3

[  I

I g 

i2  i 4

; i4  i1  i5

dt 2

o C j

2 2 in

I in 

i2  i3

---- (7)
---- (8)

 2 I o

sin  a

 I o

sin ( a  b )

International Journal of Scientific & Engineering Research Volume 2, Issue 10, Oct-2011 3

ISSN 2229-5518

3  d

 d

 o b  o a ]

4 R1 dt

4  rL dt

---(III)
Computer-simulated pulse response of the DCI gate can be obtained by solving the Eqns. (II) and (III) for an input current Iin applied as a step function at t=0 with amplitude 1.5 Ith. To solve these equations the initial conditions for a (ao) and b (bo) are to be known which can be deduced as follows:
At t = 0 from Egns. (6) and (7), we have,
Fig. 4 Simulated phase evolution vs time for a DCI gate. a and ab are the phase differences of the junctions J1 and J2, respectively. Io = 0.087 mA, Cj = 0.37 pF, R1 = R2 = 0.8  and rL = 10 .

I g  i1  i2

and i2  0

In Fig.4 we have shown the phase variations with time at different stages of the DCI gate (shown in Fig.2). The

or  ao

 sin 1 (

I g

)

2 I o

--- (a)
biasing and overdrive current conditions are as follows: Ig = 1.5 Io and Iin = 1.5 Io.
Using our concept of turn-on delay [6], the turn-on delay at each stage of the DCI has been indicated as shown in

and  ao

  bo

the Fig-2. This will give an exact physical understanding
The dynamic response of the DCI gate at each stage (shown in Fig.3) have been obtained from commputer simulation. The DCI logic gate characterstics are similar to JAWS gate, and have advantages over JAWS in the better margin and gains due to the lack of Ioff (offset) current.

Fig. 3 Simulated switching dynamics of the DCI gate. Circuit parameters used in the simulaton are from Nb/A10x/Nb Josephson technology and are given as Io =
0.087 mA, Cj = 0.37 pF, R1 = R2 = 0.8 , rL = 10 . The
swithching waveforms current flowing in the input
resistor R and the output current respectively.
of switching dynamics of the DCI logic gate.

Fig. 5a Turn-on delay of the DCI gate vs input current. TDa and TDb represent the turn-on delay variation with time at point ‘a’ and ‘b’ respectively (as shown in Fig.2)

Fig. 5b Turn-on delay of the DCI gate vs input current. TDa and TDb represent the turn-on delay variation with time at point ‘a’ and ‘b’ respectively (as shown in Fig.2)

International Journal of Scientific & Engineering Research Volume 2, Issue 10, Oct-2011 4

ISSN 2229-5518

Also we have plotted (in Fig.5a and Fig.5b) the effect of overdrive current on turn-on delay for different biasing conditions Ig = 0.75 I0, 1.5 Io and 1.95 Io. In Fig.
5a the curve (a) indicates the TD variation with overdrive at the point 'A’ (as shown in Fig.2) and the curve (b) indicates the TD variation with overdrive at the point 'B'. It can be observed from Fig.5, the turn-on delay decreases as the overdrive increases. Also, the turn-on delay increases with increase of biasing rate. So, by choosing high biasing and overdrive currents, we can minimize the turn-on delay of the DCI logic gate.
Further, for the same overdrive and biasing conditions (Ig
= 1.5 Io; Iin = 1.5 Io) the turn-on delay of the DCI gate is smaller than that of JAWS gate. . In a similar manner a thotough investigation of other resistive logic gates, DCI logic gate [7} and RCJL gate[8] have been made which gives better understanding of logic gates before they could be fabricated experimentally.

3. CONCLUSIONS

A thorough investigation of DCI logic gate has been made . The dynamic response of this logic gate is obtained by computer-simulation. The concept of our turn-on delay has been introduced which has helped us in critically ascertaining the switching speed of the logic gate. The effect of turn-on delay on overdrive current has been studied. It is observed that for low fan-outs, the DCI logic gate seems to be a better choice for logic circuit application. It is expected that the concept of turn-on delay will be able to remove confusions which are lying in the earlier investigations.

REFERENCES

[1] T. R. Gheewala, " Josephson logic devices and circuits," IEEE Trans. Electron Devices vol.ED-27, no.10, October 1980, pp.1857-1869.
[2] T. A. Fulton, S. S. Pei and L. N. Dunkleberger, " A simple high performance current switched Josephson logic," Appl. Phys. Lett. . vol.34, no.10, May 1979, pp.
709-711.
[3] T. R. Gheewala and A. Mukherjee, " Josephson direct
coupled logic (DCL)," IEDM Tech. Dig., (Washington
DC, December 3-5, 1979), pp. 482-484.
[4] J. Sone, T. Yoshida and H. Abe, " Resistor coupled
Josephson logic," Appl. Phys. Lett. vol.40, 1982, p.741.
[5] J. Sone, " Turn-on delay analysis of current-injection
Josephson circuits," J. Appl. Phys. vol.57, no.ll, June
1985, pp. 5028-5034.
[6] K. Srinivas, J. C. Biswas , " Turn-on delay of a
Josephson junction," J of Low
[7] Tempererature Physics” , vol.74, Nos. 5/6 1989 ,
pp.407-415.
[8] K. Srinivas, J. C. Biswas, “ Dynamic response of Josephson resistive logic ( JAWS) gate “ , ICECS-11, INDONESIA (SUBMITTED)
[9] K. Srinivas, J. C. Biswas, “ Dynamic response of Josephson resistive logic ( RCJL) gate “ , ICCDC-11, THAI (SUBMITTED)